HD74LS107A Datasheet, PDF (2/7 Pages) Hitachi Semiconductor – Dual J-K Negative-edge-triggered Flip-Flops(with Clear)

HD74LS107A
Block Diagram (1/2)
Q
Q
Clear
K
J
Clock
Absolute Maximum Ratings
Item
Symbol
Ratings
Supply voltage
V_CC
7
Input voltage
V_IN
7
Power dissipation
P_T
400
Storage temperature
Tstg
–65 to +150
Note: Voltage value, unless otherwise noted, are with respect to network ground terminal.
Recommended Operating Conditions
Item
Supply voltage
Output current
Operating temperature
Clock frequency
Pulse width
Clock High
Clear Low
Setup time
“H” Data
“L” Data
Hold time
Symbol
V_CC
I_OH
I_OL
Topr
f_clock
t_w
t_su
t_h
Min
4.75
—
—
–20
0
20
25
20↓
20↓
0↓
Typ
5.00
—
—
25
—
—
—
—
—
—
Max
5.25
–400
8
75
30
—
—
—
—
—
Unit
V
V
mW
°C
Unit
V
µA
mA
°C
MHz
ns
ns
ns
ns
ns
Rev.3.00, Jul.13.2005, page 2 of 6