HD151BF854_06 Datasheet, PDF (5/8 Pages) Renesas Technology Corp – 2.5 V PLL Clock Buffer for DDR Applicationjpeg

HD151BF854
Switching Characteristics
Ta = 25°C, VDD = AVDD = 2.5V
Item
Symbol Min
Typ
Max
Unit
Test Conditions & Notes
Period jitter
Half period jitter
Cycle to cycle jitter
Static phase offset
Output clock skew
Operating clock frequency
Application clock frequency
Slew rate
t_PER
—
|75|
—
ps *7, 8
t_HPER
—
|120|
—
ps *8
t_CC
—
|75|
—
ps
t_sPE
—
|150|
—
ps *4, 5
t_sk
—
150
—
ps
f_CLK(O)
60
—
210
MHz *1, 2
f_CLK(A)
80
166
210
MHz *1, 3
1.0
—
2.0
V/ns 20% to 80%
Stabilization time
—
—
0.1
ms *6
Notes: Target of design, not 100% tested in production.
1. The PLL must be able to handle spread spectrum induced skew. (the specification for this frequency
modulation can be found in the latest Intel PC100 Registered DIMM specification)
2. Operating clock frequency indicates a range over which the PLL must be able to lock, but in which it is not
required to meet the other timing parameters. (Used for low speed system debug.)
3. Application clock frequency indicates a range over which the PLL must meet all timing parameters.
4. Assumes equal wire length and loading on the clock output and feedback path.
5. Static phase offset does not include jitter.
6. Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of it’s feedback signal
to it’s reference signal after power on.
7. Period jitter defines the largest variation in clock period, around a nominal clock period.
8. Period jitter and half period jitter are separate specifications that must be met independently of each other.
Rev.5.00 Apr 07, 2006 page 5 of 7