HD151BF854_06 Datasheet, PDF (4/8 Pages) Renesas Technology Corp – 2.5 V PLL Clock Buffer for DDR Applicationjpeg

HD151BF854
Recommended Operating Conditions
Item
Symbol Min
Typ
Max
Supply voltage
AVDD
2.3
2.5
2.7
Output supply voltage
VDD
2.3
2.5
2.7
DC input signal voltage
–0.3
— VDD+0.3
High level input voltage
V_IH
1.7
—
3.6
High level input voltage
V_IH
1.7
— VDD+0.3
Low level input voltage
V_IL
–0.3
—
0.7
Output differential cross point voltage
V_OX 0.5×VDD
—
0.5×VDD
–0.2
+0.2
Output current
I_OH
—
—
–12
I_OL
—
—
12
Input clock slew rate
SR
1
—
—
Operating temperature
T_a
0
—
70
Note: Unused inputs must be held high or low to prevent them from floating.
Unit
Conditions
V
V
V All pins
V CLKIN
V FBIN
V CLKIN, FBIN
V
mA
V/ns
°C
Electrical Characteristics
Item
Symbol Min
Typ *¹
Max
Unit
Test Conditions
Input clamp voltage
(All inputs)
V_IK
—
—
–1.2
V I_I = –18 mA, VDD = 2.3 V
Output voltage
V_OH
VDD–0.2
—
—
V I_OH = –100 µA, VDD = 2.3 to 2.7 V
1.7
—
VDD
I_OH = –12 mA, VDD = 2.3 V
V_OL
—
—
0.2
I_OL = 100 µA, VDD = 2.3 to 2.7 V
Input current
—
—
0.6
I_OL = 12 mA, VDD = 2.3 V
I_I
–10
—
10
µA V_I = 0 V or 2.7 V,
VDD = 2.7 V, CLKIN, FBIN
Analog supply current
AI_CC
—
—
12
mA VDD = AVDD = 2.7 V,
170 MHz
Dynamic supply current
DI_CC
—
250
300
mA VDD = AVDD = 2.7 V, 170 MHz,
All Yn, Yn, = open
Input capacitance*²
C_I
2.5
—
3.5
pF CLKIN and FBIN
Delta input capacitance*²
C_Di
–0.25
—
0.25
pF
Notes: 1. For conditions shown as Min or Max, use the appropriate value specified under recommended operating
conditions.
2. Target of design, not 100% tested in production.
Rev.5.00 Apr 07, 2006 page 4 of 7