HD151BF854_06 Datasheet, PDF (1/8 Pages) Renesas Technology Corp – 2.5 V PLL Clock Buffer for DDR Applicationjpeg

HD151BF854
2.5 V PLL Clock Buffer for DDR Application
REJ03D0809-0500
(Previous: ADE-205-696D)
Rev.5.00
Apr 07, 2006
Description
The HD151BF854 is a high-performance, low-skew, low-jitter, PLL clock buffer. It is specifically designed for use
with DDR (Double Data Rate) PC motherboard application.
Features
• Designed for DDR200/266/333/400 PC mother board clock buffering
• Supports 60 MHz to 210 MHz operation range
• Distributes one to six differential clock outputs pairs
• Spread spectrum clock compatible
• External feedback pin (FBIN) is used to synchronize the outputs to the clock input
• Supports 2.5 V analog supply voltage (AVDD), and 2.5 V VDD
• Ordering Information
Part Name
Package Type
HD151BF854SSEL SSOP-28 pin
Package Code
(Previous Code)
PRSP0028JA-A
(FP-28DSAV)
Package
Abbreviation
SS
Taping Abbreviation
(Quantity)
EL (1,000 pcs / Reel)
Key Specifications
• Supply voltages: VDD = AVDD = 2.5 V±0.2 V
• Output clock cycle to cycle jitter = ±75 ps
• Output clock pin to pin skew = 150 ps
Function Table
Inputs
AVDD
CLK
Yn
GND
L
L
GND
H
H
2.5 V (typ.)
L
L
2.5 V (typ.)
H
H
H: High level
L: Low level
Outputs
Yn
H
L
H
L
FBOUT
L
H
L
H
PLL
Bypass / Off
Bypass / Off
Running
Running
Rev.5.00 Apr 07, 2006 page 1 of 7