HD151BF854_06 Datasheet, PDF (2/8 Pages) Renesas Technology Corp – 2.5 V PLL Clock Buffer for DDR Applicationjpeg

HD151BF854
Pin Arrangement
Y0 1
Y0 2
VDD 3
Y1 4
Y1 5
GND 6
NC 7
CLKIN 8
NC 9
AVDD 10
AGND 11
VDD 12
Y2 13
Y2 14
28 GND
27 Y5
26 Y5
25 Y4
24 Y4
23 VDD
22 NC
21 NC
20 FBIN
19 FBOUT
18 NC
17 Y3
16 Y3
15 GND
(Top view)
Pin Functions
Pin name
AGND
AVDD
CLKIN
FBIN
FBOUT
GND
VDD
Y
Y
NC
No.
11
10
Type
Ground
Power
8
Input
20
Input
19
Output
6, 15, 28 Ground
3, 12, 23 Power
2, 4, 13, Output
17, 24, 26
1, 5, 14, Output
16, 25, 27
7, 9, 18, 21, NC
22
Description
Analog ground. AGND provides the ground reference for the analog circuitry.
Analog power supply. AVDD provides the power reference for the analog
circuitry. In addition, AVDD can be used to bypass the PLL for test purposes.
When AVDD is strapped to ground, PLL is bypassed and CLK is buffered
directly to the device outputs.
Clock input. CLKIN provides the clock signal to be distributed by the
HD151BF854 clock buffer. CLK is used to provide the reference signal to the
integrated PLL that generates the clock output signals. CLK must have a
fixed frequency and fixed phase for the PLL to obtain phase lock. Once the
circuit is powered up and a valid CLK signal is applied, a stabilization time is
required for the PLL to phase lock the feedback signal to its reference signal.
Feedback input. FBIN provides the feedback signal to the internal PLL. FBIN
must be hard-wired to FBOUT to complete the PLL. The integrated PLL
synchronizes CLKIN and FBIN so that there is nominally zero phase error
between CLKIN and FBIN.
Feedback output. FBOUT is dedicated for external feedback. It switches at
the same frequency as CLK. When externally wired to FBIN, FBOUT
completes the feedback loop of the PLL.
Ground
Power supply
Clock outputs. (+Clock) These outputs provide low-skew copies of CLK.
Bar clock outputs. (–Clock) These outputs provide low-skew copies of CLK.
Don’t connect any VDD or GND.
Rev.5.00 Apr 07, 2006 page 2 of 7