HD151BF854_06 Datasheet, PDF (3/8 Pages) Renesas Technology Corp – 2.5 V PLL Clock Buffer for DDR Applicationjpeg

HD151BF854
Logic Diagram
AV_DD ¹⁰
Test
Logic
CLKIN ⁸
PLL
FBIN ²⁰
2 _Y0
1
Y0
4 _Y1
5 _Y1
13 _Y2
14
Y2
17 _Y3
16
Y3
24 _Y4
25
Y4
26 _Y5
27
Y5
19 _FBOUT
Note: All inputs and outputs are associated with V_DDQ = 2.5 V.
Absolute Maximum Ratings
Item
Symbol
Ratings
Unit
Conditions
Supply voltage
VDD
–0.5 to 3.6
V
Input voltage
V_IC
–0.5 to 3.6
V
CLKIN
Output voltage *¹
V_I
–0.5 to VDD+0.5
V
V_O
–0.5 to VDD+0.5
V
Input clamp current
I_IK
–50
mA
V_I < 0
Output clamp current
I_OK
–50
mA
V_O < 0
Continuous output current
I_O
±50
mA
V_O = 0 to VDD
Maximum power dissipation
0.7
W
at Ta = 55°C (in still air)
Storage temperature
T_stg
–65 to +150
°C
Notes: Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those indicated under “recommended operating conditions” is not implied. Exposure to absolute maximum
rated conditions for extended periods may affect device reliability.
1. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings
are observed.
Rev.5.00 Apr 07, 2006 page 3 of 7