R8C33A Datasheet, PDF (462/617 Pages) Renesas Technology Corp – MCU M16C FAMILY / R8C/Tiny SERIES

Under development ^{Preliminary specification}
Specifications in this manual are tentative and subject to change.
R8C/33A Group
26. Hardware LIN
A
Timer RA Set the timer to start counting
TSTART bit in TRACR register ← 1
Timer RA Read the count status flag
TCSTF flag in TRACR register
NO
TCSTF = 1?
YES
Hardware LIN Read the Synch Break detection flag
SBDCT flag in LINST register
NO
SBDCT = 1?
YES
Timer RA Set the timer to stop counting
TSTART bit in TRACR register ← 0
Timer RA Read the count status flag
TCSTF flag in TRACR register
NO
TCSTF = 0?
YES
UART0 Communication via UART0
TE bit in U0C1 register ← 1
U0TB register ← 0055h
UART0 Communication via UART0
U0TB register ← ID field
A Synch Break for timer RA is
generated.
After writing 1 to the TSTART bit,
if registers TRAPRE and TRA for
timer RA are not read or the register
settings are not changed, reading 1
from the TCSTF flag can be omitted.
Zero or one cycle of the timer RA
count source is required after timer
RA starts counting before the TCSTF
flag is set to 1.
A timer RA interrupt can be used to
end Synch Break generation.
One or two cycles of the CPU clock
are required after Synch Break
generation ends before the SBDCT
flag is set to 1.
After a Synch Break for timer RA is
generated, stop the timer count.
After writing 0 to the TSTART bit,
if registers TRAPRE and TRA for
timer RA are not read or the register
settings are not changed, reading 0
from the TCSTF flag can be omitted.
Zero or one cycle of the timer RA
count source is required after timer
RA stops counting before the TCSTF
flag is set to 0.
The Synch Field is transmitted.
The ID field is transmitted.
Figure 26.4 Header Field Transmission Flowchart Example (2)
REJ09B0455-0010 Rev.0.10 Feb 29, 2008
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