R8C33A Datasheet, PDF (328/617 Pages) Renesas Technology Corp – MCU M16C FAMILY / R8C/Tiny SERIES

Under development ^{Preliminary specification}
Specifications in this manual are tentative and subject to change.
R8C/33A Group
21. Serial Interface (UARTi (i = 0 or 1))
21.2.4 UARTi Transmit/Receive Control Register 0 (UiC0) (i = 0 or 1)
Address 00A4h (U0C0), 0164h (U1C0)
Bit b7
b6
b5
b4
b3
b2
Symbol UFORM CKPOL NCH
—
TXEPT
—
After Reset 0
0
0
0
1
0
b1
CLK1
0
b0
CLK0
0
Bit Symbol
Bit Name
Function
R/W
b0
CLK0 _{BRG count source select bit} ^{(1) b1 b0}
b1 CLK1
0 0: f1 selected
0 1: f8 selected
R/W
R/W
1 0: f32 selected
1 1: fC selected
b2
— Reserved bit
Set to 0.
R/W
b3 TXEPT Transmit register empty flag
0: Data present in the transmit register
R
(transmission in progress)
1: No data in the transmit register
(transmission completed)
b4
— Nothing is assigned. If necessary, set to 0. When read, the content is 0.
—
b5
NCH Data output select bit
0: TXDi pin set to CMOS output
R/W
1: TXDi pin set to N-channel open-drain output
b6 CKPOL CLK polarity select bit
0: Transmit data output at the falling edge and receive R/W
data input at the rising edge of the transfer clock
1: Transmit data output at the rising edge and receive
data input at the falling edge of the transfer clock
b7 UFORM Transfer format select bit
0: LSB first
R/W
1: MSB first
Note:
1. If the BRG count source is switched, set the UiBRG register again.
21.2.5 UARTi Transmit/Receive Control Register 1 (UiC1) (i = 0 or 1)
Address 00A5h (U0C1), 0165h (U1C1)
Bit b7
b6
b5
b4
b3
b2
b1
b0
Symbol —
—
UiRRM UiIRS
RI
RE
TI
TE
After Reset 0
0
0
0
0
0
1
0
Bit Symbol
Bit Name
Function
R/W
b0
TE Transmit enable bit
0: Transmission disabled
R/W
1: Transmission enabled
b1
TI Transmit buffer empty flag
0: Data present in the UiTB register
R
1: No data in the UiTB register
b2
RE Receive enable bit
0: Reception disabled
R/W
1: Reception enabled
b3
RI _{Receive complete flag} ⁽¹⁾
0: No data in the UiRB register
R
1: Data present in the UiRB register
b4 UiIRS UARTi transmit interrupt source
0: Transmission buffer empty (TI = 1)
R/W
select bit
1: Transmission completed (TXEPT = 1)
b5 UiRRM UARTi continuous receive mode 0: Continuous receive mode disabled
R/W
enable bit ⁽²⁾
1: Continuous receive mode enabled
b6
— Nothing is assigned. If necessary, set to 0. When read, the content is 0.
—
b7
—
Notes:
1. The RI bit is set to 0 when the higher byte of the UiRB register is read.
2. In UART mode, set the UiRRM bit to 0 (continuous receive mode disabled).
REJ09B0455-0010 Rev.0.10 Feb 29, 2008
Page 300 of 586