R8C33A Datasheet, PDF (404/617 Pages) Renesas Technology Corp – MCU M16C FAMILY / R8C/Tiny SERIES

Under development ^{Preliminary specification}
Specifications in this manual are tentative and subject to change.
R8C/33A Group
24. Synchronous Serial Communication Unit (SSU)
24.3.3 Interrupt Requests
Synchronous serial communication unit has five interrupt requests: transmit data empty, transmit end, receive
data full, overrun error, and conflict error. Since these interrupt requests are assigned to the synchronous serial
communication unit interrupt vector table, determining interrupt sources by flags is required.
Table 24.3 shows the Synchronous Serial Communication Unit Interrupt Requests.
Table 24.3 Synchronous Serial Communication Unit Interrupt Requests
Interrupt Request
Transmit data empty
Transmit end
Receive data full
Overrun error
Conflict error
Abbreviation
TXI
TEI
RXI
OEI
CEI
Generation Condition
TIE = 1, TDRE = 1
TEIE = 1, TEND = 1
RIE = 1, RDRF = 1
RIE = 1, ORER = 1
CEIE = 1, CE = 1
CEIE, RIE, TEIE and TIE: Bits in SSER register
ORER, RDRF, TEND and TDRE: Bits in SSSR register
If the generation conditions in Table 24.3 are met, a synchronous serial communication unit interrupt request is
generated. Set each interrupt source to 0 by a synchronous serial communication unit interrupt routine.
However, the TDRE and TEND bits are automatically set to 0 by writing transmit data to the SSTDR register and
the RDRF bit is automatically set to 0 by reading the SSRDR register. In particular, the TDRE bit is set to 1 (data
transmitted from registers SSTDR to SSTRSR) at the same time transmit data is written to the SSTDR register.
Setting the TDRE bit to 0 (data not transmitted from registers SSTDR to SSTRSR) can cause an additional byte of
data to be transmitted.
REJ09B0455-0010 Rev.0.10 Feb 29, 2008
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