R8C33A Datasheet, PDF (379/617 Pages) Renesas Technology Corp – MCU M16C FAMILY / R8C/Tiny SERIES

Under development ^{Preliminary specification}
Specifications in this manual are tentative and subject to change.
R8C/33A Group
22. Serial Interface (UART2)
22.5.6 SDA Input
When the IICM2 bit is set to 0, the 1st to 8th bits (D7 to D0) of received data are stored in bits b7 to b0 in the
U2RB register. The 9th bit (D8) is ACK or NACK.
When the IICM2 bit is set to 1, the 1st to 7th bits (D7 to D1) of received data are stored in bits b6 to b0 in the
U2RB register and the 8th bit (D0) is stored in bit b8 in the U2RB register. Even when the IICM2 bit is set to 1,
if the CKPH bit is 1, the same data as when the IICM2 bit is 0 can be read by reading the U2RB register after
the rising edge of 9th bit of the clock.
22.5.7 ACK and NACK
If the STSPSEL bit in the U2SMR4 register is set to 0 (start and stop conditions not output) and the ACKC bit
in the U2SMR4 register is set to 1 (ACK data output), the value of the ACKD bit in the U2SMR4 register is
output from the SDA2 pin.
If the IICM2 bit is set to 0, a NACK interrupt request is generated if the SDA2 pin remains high at the rising
edge of the 9th bit of transmit clock pulse. An ACK interrupt request is generated if the SDA2 pin is low at the
rising edge of the 9th bit of the transmit clock.
If ACK2 (UART2 reception) is selected to generate a DTC request source, a DTC transfer can be activated by
detection of an acknowledge.
22.5.8 Initialization of Transmission/Reception
If a start condition is detected while the STAC bit is set to 1 (UART2 initialization enabled), the serial interface
operates as described below.
• The transmit shift register is initialized, and the contents of the U2TB register are transferred to the transmit
shift register. In this way, the serial interface starts sending data when the next clock pulse is applied.
However, the UART2 output value does not change state and remains the same as when a start condition was
detected until the first bit of data is output in synchronization with the input clock.
• The receive shift register is initialized, and the serial interface starts receiving data when the next clock pulse
is applied.
• The SWC bit is set to 1 (SCL wait output enabled). Consequently, the SCL2 pin is pulled low at the falling
edge of the 9th clock pulse.
Note that when UART2 transmission/reception is started using this function, the TI bit does not change state.
Select the external clock as the transfer clock to start UART2 transmission/reception with this setting.
REJ09B0455-0010 Rev.0.10 Feb 29, 2008
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