R8C_08 Datasheet, PDF (46/487 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MCU R8C FAMILY / R8C/2x SERIES

R8C/26 Group, R8C/27 Group
5. Resets
Option Function Select Register⁽¹⁾
b7 b6 b5 b4 b3 b2 b1 b0
1
1
Symbol
OFS
Bit Symbol
Address
0FFFFh
Bit Name
When Shipping
FFh⁽³⁾
Function
RW
Watchdog timer start 0 : Starts w atchdog timer automatically after reset
WDTON _{select bit}
1 : Watchdog timer is inactive after reset
RW
—
Reserved bit
Set to 1.
(b1)
RW
ROM code protect
0 : ROM code protect disabled
ROMCR _{disabled bit}
1 : ROMCP1 enabled
RW
ROM code protect bit 0 : ROM code protect enabled
ROMCP1
1 : ROM code protect disabled
RW
—
Reserved bit
Set to 1.
(b4)
RW
Voltage detection 0
circuit start bit^{(2, 4)}
LVD0ON
0 : Voltage monitor 0 reset enabled after hardw are
reset
1 : Voltage monitor 0 reset disabled after hardw are
RW
reset
Voltage detection 1
circuit start bit^{(5, 6)}
LVD1ON
0 : Voltage monitor 1 reset enabled after hardw are
reset
1 : Voltage monitor 1 reset disabled after hardw are
RW
reset
Count source protect 0 : Count source protect mode enabled after reset
CSPROINI ^{mode after reset select 1 : Count source protect mode disabled after reset}
RW
bit
NOTES:
1. The OFS register is on the flash memory. Write to the OFS register w ith a program. After w riting is completed, do not
w rite additions to the OFS register.
2. The LVD0ON bit setting is valid only by a hardw are reset. To use the pow er-on reset, set the LVD0ON bit to 0
(voltage monitor 0 reset enabled after hardw are reset).
3. If the block including the OFS register is erased, FFh is set to the OFS register.
4. For N, D version only. For J, K version, set the LVD0ON bit to 1 (voltage monitor 0 reset disabled after hardw are
reset).
5. The LVD1ON bit setting is valid only by a hardw are reset. When the pow er-on reset function is used, set the
LVD1ON bit to 0 (voltage monitor 1 reset enabled after hardw are reset).
6. For J, K version only. For N, D version, set the LVD1ON bit to 1 (voltage monitor 1 reset disabled after hardw are
reset).
Figure 5.5 OFS Register
Rev.2.10 Sep 26, 2008 Page 27 of 453
REJ09B0278-0210