R8C_08 Datasheet, PDF (273/487 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MCU R8C FAMILY / R8C/2x SERIES

R8C/26 Group, R8C/27 Group
15. Serial Interface
Table 15.5 Registers Used and Settings for UART Mode
Register
UiTB
UiRB
UiBRG
UiMR
UiC0
UiC1
Bit
0 to 8
0 to 8
OER, FER, PER, SUM
0 to 7
SMD2 to SMD0
CKDIR
STPS
PRY, PRYE
CLK0, CLK1
TXEPT
NCH
CKPOL
UFORM
TE
TI
RE
RI
UiIRS
UiRRM
Function
Set transmit data⁽¹⁾
Receive data can be read^{(1, 2)}
Error flag
Set a bit rate
Set to 100b when transfer data is 7 bits long.
Set to 101b when transfer data is 8 bits long.
Set to 110b when transfer data is 9 bits long.
Select the internal clock or external clock
Select the stop bit
Select whether parity is included and whether odd or even
Select the count source for the UiBRG register
Transmit register empty flag
Select TXDi pin output mode
Set to 0
LSB first or MSB first can be selected when transfer data is 8 bits long.
Set to 0 when transfer data is 7 or 9 bits long.
Set to 1 to enable transmit
Transmit buffer empty flag
Set to 1 to enable receive
Receive complete flag
Select the factor of UARTi transmit interrupt
Set to 0
i = 0 or 1
NOTES:
1. The bits used for transmit/receive data are as follows: Bits 0 to 6 when transfer data is 7 bits long; bits 0 to 7
when transfer data is 8 bits long; bits 0 to 8 when transfer data is 9 bits long.
2. The following bits are undefined: Bits 7 and 8 when transfer data is 7 bits long; bit 8 when transfer data is 8 bits
long.
Table 15.6 lists the I/O Pin Functions in UART Mode. After the UARTi (i = 0 or 1) operating mode is selected, the
TXDi pin outputs “H” level (If the NCH bit is set to 1 (N-channel open-drain output), this pin is in a high-
impedance state) until transfer starts.
Table 15.6 I/O Pin Functions in UART Mode
Pin name
Function
TXD0 (P1_4) Output serial data
RXD0 (P1_5) Input serial data
CLK0 (P1_6) Programmable I/O Port
Input transfer clock
TXD1 (either
P0_0, P3_6,
or P3_7)
RXD1 (either
P3_6, P3_7,
or P4_5)
Output serial data
Input serial data
CLK1 (P0_5) Programmable I/O Port
Input transfer clock
Selection Method
(Cannot be used as a port when performing reception only)
PD1_5 bit in PD1 register = 0
(P1_5 can be used as an input port when performing transmission only)
CKDIR bit in U0MR register = 0
CKDIR bit in U0MR register = 1
PD1_6 bit in PD1 register = 0
Set registers PINSR1 and PMR (refer to Figure 15.7 Registers PINSR1
and PMR)
(Cannot be used as a port when performing reception only)
Set registers PINSR1 and PMR (refer to Figure 15.7 Registers PINSR1
and PMR)
Corresponding bit in each port direction register = 0
(Can be used as an input port when performing transmission only)
CKDIR bit in U1MR register = 0
PD0_5 bit in PD0 register = 0
CKDIR bit in U1MR register = 1
Rev.2.10 Sep 26, 2008 Page 254 of 453
REJ09B0278-0210