M16C64A_15 Datasheet, PDF (45/92 Pages) Renesas Technology Corp – RENESAS MCU

M16C/64A Group
5. Electrical Characteristics
5.1.5 Flash Memory Electrical Characteristics
Table 5.8 CPU Clock When Operating Flash Memory (f_(BCLK))
V_CC1 = 2.7 to 5.5 V, T_opr = -20°C to 85°C/-40°C to 85°C unless otherwise specified.
Symbol
Parameter
Conditions
Standard
Unit
Min.
Typ.
Max.
-
CPU rewrite mode
10 ^{(1) MHz}
f(SLOW_R) Slow read mode
5 ^{(3) MHz}
-
Low current consumption read mode
fC(32.768) 35
kHz
-
Data flash read
2.7 V ≤ V_CC1 ≤ 3.0 V
3.0 V < V_CC1 ≤ 5.5 V
16 ⁽²⁾
20 ⁽²⁾
MHz
MHz
Notes:
1. Set the PM17 bit in the PM1 register to 1 (one wait).
2. When the frequency is over this value, set the FMR17 bit in the FMR1 register to 0 (one wait) or the PM17 bit in
the PM1 register to 1 (one wait)
3. Set the PM17 bit in the PM1 register to 1 (one wait). When using 125 kHz on-chip oscillator clock or sub clock as
the CPU clock source, a wait is not necessary.
Table 5.9 Flash Memory (Program ROM 1, 2) Electrical Characteristics
V_CC1 = 2.7 to 5.5 V at T_opr = 0°C to 60°C (option: -40°C to 85°C), unless otherwise specified.
Symbol
-
-
-
-
-
-
-
Parameter
Conditions
Min.
Program and erase cycles ^{(1), (3), (4) V}_CC1 ^{= 3.3 V, T}_opr ^{= 25°C}
1,000 ⁽²⁾
2 word program time
Lock bit program time
V_CC1 = 3.3 V, T_opr = 25°C
V_CC1 = 3.3 V, T_opr = 25°C
Block erase time
V_CC1 = 3.3 V, T_opr = 25°C
Program, erase voltage
2.7
Read voltage
T_opr= -20°C to 85°C/-40°C to 85°C 2.7
Program, erase temperature
0
Standard
Typ.
150
70
0.2
Max.
4000
3000
3.0
5.5
5.5
60
Unit
times
μs
μs
s
V
V
°C
t_PS
Flash memory circuit stabilization wait time
-
Data hold time ⁽⁶⁾
Ambient temperature = 55°C
20
50
μs
year
Notes:
1. Definition of program and erase cycles:
The program and erase cycles refer to the number of per-block erasures. If the program and erase cycles are n
(n = 1,000), each block can be erased n times. For example, if a block is erased after writing 2 word data 16,384
times, each to a different address, this counts as one program and erase cycles. Data cannot be written to the
same address more than once without erasing the block (rewrite prohibited).
2. Cycles to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed).
3. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing
to sequential addresses in turn so that as much of the block as possible is used up before performing an erase
operation. It is advisable to retain data on the erasure cycles of each block and limit the number of erase
operations to a certain number.
4. If an error occurs during block erase, attempt to execute the clear status register command, then execute the
block erase command at least three times until the erase error does not occur.
5. Customers desiring program/erase failure rate information should contact a Renesas Electronics sales office.
6. The data hold time includes time that the power supply is off or the clock is not supplied.
R01DS0032EJ0200 Rev.2.00
Feb 07, 2011
Page 45 of 88