PD17225_15 Datasheet, PDF (43/86 Pages) Renesas Technology Corp – 4-BIT SINGLE-CHIP MICROCONTROLLER FOR SMALL GENERAL-PURPOSE INFRARED REMOTE CONTROL TRANSMITTER

µPD17225, 17226, 17227, 17228
7.2 Hardware of Interrupt Control Circuit
This section describes the flags of the interrupt control circuit.
(1) Interrupt request flag and interrupt enable flag
The interrupt request flag (IRQ×××) is set to 1 when an interrupt request is generated, and is automatically
cleared to 0 when the interrupt processing is excuted.
An interrupt enable flag (IP×××) is provided to each interrupt request flag. When the IPxxx flag is 1, the interrupt
is enabled; when it is 0, the interrupt is disabled.
(2) EI/DI instruction
Whether an accepted interrupt is executed or not is specified by the EI or DI instruction.
When the EI instruction is executed, INTE (interrupt enable flag), which enables the interrupt, is set to 1. The
INTE flag is not registered on the register file. Consequently, the status of this flag cannot be checked by
an instruction.
The DI flag clears the INTE flag to 0 to disable all the interrupts.
The INTE flag is also cleared to 0 at reset, disabling all the interrupts.
Table 7-2. Interrupt Request Flags and Interrupt Enable Flag
Interrupt
Request Flag
IRQTM
IRQ
IRQBTM
Signal Setting Interrupt Request Flag
Reset by 8-bit timer.
Set when edge of INT pin input signal is detected
Reset by basic interval timer.
Interrupt
Enable Flag
IPTM
IP
IPBTM
7.2.1 INT
This flag reads the INT pin status.
When a high level is input to the INT pin, this flag is set to “1”; when a low level is input, the flag is reset to “0”.
3
2
0
0
1
0
Address On reset
R/W
0
INT
RF : 0FH Undefined
R
INT INT Pin Level Detection
0
INT pin : Low level
1
INT pin : High level
Data Sheet U12643EJ2V0DS00
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