PD17225_15 Datasheet, PDF (17/86 Pages) Renesas Technology Corp – 4-BIT SINGLE-CHIP MICROCONTROLLER FOR SMALL GENERAL-PURPOSE INFRARED REMOTE CONTROL TRANSMITTER

µPD17225, 17226, 17227, 17228
2.4 Data Memory (RAM)
Data memory (random access memory) stores data for operations and control. It can be read-/write-accessed by
instructions.
2.4.1 Memory configuration
Figure 2-4 shows the configuration of the data memory (RAM).
The data memory consists of two “banks”: BANK0 and BANK1.
In each bank, every 4 bits of data is assigned an address. The high-order 3 bits of the address indicate a “row address”
and the low-order 4 bits of the address indicate a “column address”. For example, a data memory location indicated by
row address 1H and column address 0AH is termed a data memory location at address 1AH. Each address stores data
of 4 bits (= a “nibble”).
In addition, the data memory is divided into following six functional blocks:
(1) System register (SYSREG)
A system register (SYSREG) is resident on addresses 74H to 7FH (12 nibbles long) of each bank. In other
nibbles, each bank has a system register at its addresses 74H to 7FH.
(2) Data buffer (DBF)
A data buffer is resident on addresses 0CH to 0FH (4 nibbles long) of bank 0 of data memory.
The reset value is 0320H.
(3) General register (GR)
A general register is resident on any row (16 nibbles long) of any bank of data memory.
The row address of the general register is pointed by the general pointer (RP) in the system register (SYSREG).
(4) Port register
A port data register is resident on addresses 6FH, and 70H to 73H (5 nibbles) of BANK0 of data memory.
No data can be written to the addresses 70H to 73H of BANK1 (the values of addresses 70H to 73H of BANK0
are read in this case).
µPD17225 and 17226 are not provided with BANK1.
Data Sheet U12643EJ2V0DS00
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