NP82N04PDG_15 Datasheet, PDF (4/10 Pages) Renesas Technology Corp – SWITCHING N-CHANNEL POWER MOS FET

ELECTRICAL CHARACTERISTICS (TA = 25°C)
CHARACTERISTICS
SYMBOL
TEST CONDITIONS
Zero Gate Voltage Drain Current
Gate Leakage Current
Gate to Source Threshold Voltage
IDSS
IGSS
VGS(th)
VDS = 40 V, VGS = 0 V
VGS = ±20 V, VDS = 0 V
VDS = VGS, ID = 250 μA
Forward Transfer Admittance
| yfs | VDS = 10 V, ID = 41 A
Drain to Source On-state Resistance
RDS(on)1 VGS = 10 V, ID = 41 A
RDS(on)2 VGS = 4.5 V, ID = 41 A
Input Capacitance
Ciss
VDS = 25 V
Output Capacitance
Coss
VGS = 0 V
Reverse Transfer Capacitance
Crss
f = 1 MHz
Turn-on Delay Time
td(on)
VDD = 20 V, ID = 41 A
Rise Time
tr
VGS = 10 V
Turn-off Delay Time
td(off)
RG = 0 Ω
Fall Time
tf
Total Gate Charge
QG
VDD = 32 V
Gate to Source Charge
QGS
VGS = 10 V
Gate to Drain Charge
QGD
ID = 82 A
Body Diode Forward Voltage
VF(S-D) IF = 82 A, VGS = 0 V
Reverse Recovery Time
Reverse Recovery Charge
trr
IF = 82 A, VGS = 0 V
Qrr
di/dt = 100 A/μs
NP82N04PDG
MIN. TYP. MAX. UNIT
1
μA
±100 nA
1.4 1.8 2.5 V
20 47
S
2.9 3.5 mΩ
4.1 8.0 mΩ
6000 9000 pF
580 870 pF
370 670 pF
26 60 ns
68 170 ns
73 150 ns
11 30 ns
100 150 nC
19
nC
32
nC
0.9 1.5 V
43
ns
47
nC
TEST CIRCUIT 1 AVALANCHE CAPABILITY
D.U.T.
RG = 25 Ω
L
PG.
50 Ω
VDD
VGS = 20 → 0 V
BVDSS
IAS
ID
VDD
VDS
Starting Tch
TEST CIRCUIT 3 GATE CHARGE
D.U.T.
IG = 2 mA
RL
PG.
50 Ω
VDD
TEST CIRCUIT 2 SWITCHING TIME
D.U.T.
RG
PG.
VGS
0
τ
τ = 1 μs
Duty Cycle ≤ 1%
RL
VDD
VGS
VGS
Wave Form
10%
0
VDS
90%
VDS
VDS
0
Wave Form
td(on)
VGS
90%
90%
10% 10%
tr td(off) tf
ton
toff
2
Data Sheet D18396EJ1V0DS