N0400P Datasheet, PDF (4/10 Pages) Renesas Technology Corp – MOS FIELD EFFECT TRANSISTOR

N0400P
ELECTRICAL CHARACTERISTICS (TA = 25°C)
CHARACTERISTICS
SYMBOL
TEST CONDITIONS
Zero Gate Voltage Drain Current
IDSS
Gate Leakage Current
IGSS
Gate to Source Cut-off Voltage
Forward Transfer Admittance ^Note
Drain to Source On-state Resistance ^Note
VGS(off)
| yfs |
RDS(on)1
VDS = −40 V, VGS = 0 V
VGS = m20 V, VDS = 0 V
VDS = −10 V, ID = −1 mA
VDS = −10 V, ID = −7.5 A
VGS = −4.5 V, ID = −7.5 A
Input Capacitance
RDS(on)2
Ciss
VGS = −2.5 V, ID = −7.5 A
VDS = −10 V,
Output Capacitance
Coss
VGS = 0 V,
Reverse Transfer Capacitance
Crss
f = 1 MHz
Turn-on Delay Time
Rise Time
Turn-off Delay Time
td(on)
tr
td(off)
VDD = −20 V, ID = −7.5 A,
VGS = −4.5 V,
RG = 0 Ω
Fall Time
Total Gate Charge
Gate to Source Charge
tf
QG
VDD = −32 V,
QGS
VGS = −4.5 V,
Gate to Drain Charge
Body Diode Forward Voltage ^Note
Reverse Recovery Time
Reverse Recovery Charge
QGD
VF(S-D)
trr
Qrr
ID = −15 A
IF = −15 A, VGS = 0 V
IF = −15 A, VGS = 0 V,
di/dt = −100 A/μs
Note Pulsed: PW ≤ 350 μs, Duty Cycle ≤ 2%
MIN.
−0.5
6.0
TYP.
−1.0
31
40
1400
200
155
11
16
104
93
16
3
7
0.94
32
33
MAX.
−10
m10
−1.5
40
73
1.5
UNIT
μA
μA
V
S
mΩ
mΩ
pF
pF
pF
ns
ns
ns
ns
nC
nC
nC
V
ns
nC
TEST CIRCUIT 1 AVALANCHE CAPABILITY
D.U.T.
RG = 25 Ω
L
PG.
50 Ω
VDD
VGS = −12 → 0 V
−
IAS ^BVDSS
VDS
ID
VDD
Starting Tch
TEST CIRCUIT 2 SWITCHING TIME
D.U.T.
RG
PG.
VGS(−)
0
τ
τ = 1 μs
Duty Cycle ≤ 1%
RL
VDD
VGS(−)
VGS
Wave Form
0 ^10%
VDS(−)
90%
VDS
VDS
Wave Form ⁰
td(on)
VGS
90%
90%
10% 10%
tr td(off)
tf
ton
toff
TEST CIRCUIT 3 GATE CHARGE
D.U.T.
IG = −2 mA
RL
PG.
50 Ω
VDD
2
Data Sheet D19676EJ1V0DS