HD49815TF Datasheet, PDF (4/22 Pages) Hitachi Semiconductor – Digital Camera Signal Processor

HD49815TF
Pin Description
Pin No.
1
2
3
4
5
6
7
8
9
Symbol
XSUB
DKF_LD
T_CP
TY_K
SDI
SDCK
SLD
SDO
EP (1)
Pin Name
CCD shutter pulse
Line input LD
Test
Title SW
State data input
State data clock
State data load pulse
AWB, AE, data output
AE window pulse 1
10
EP (2)
AE window pulse 2
11
BF
12
HD_IN
13
M_CK
Burst flag
External CSYNC input
Microprocessor clock
14
V_DD
V_CC2
15
V_SS
GND
16
FV
Field vertical output
17
HD
HD output
18
CBLK
Blanking pulse
19
CSYNC
SYNC output
20
SCBLK
SC blanking pulse
21
HSYNC
Horizontal SYNC
22
ID
Identity
23
IDP
Identity pulse
24
V_DD
V_CC2
25
V_SS
GND
26
X1I
X’tal 1 input
27
X1O
X’tal 1 output
28
IDS
Line ID reset input
29
MCK_S
MCK output SW
30
RESET
Reset
31
PLL_N
PLL negative
32
PLL_P
PLL positive
33
VR
Vertical reset
34
X2I
X’tal 2 input
35
X2O
X’tal 2 output
36
FSC
Sub carrier frequency
37
V_SS
GND
38
AV_DD
Analog V_CC2
39
V_SS
GND
40
AV_DD
Analog V_CC2
41
V_SS
GND
42
C_OUT
C analog signal output
43
CBU
Current buffer upper
44
CBL
Current buffer lower
45
REXT
Reference resister EXT
I/O
Description
O CCD control pulse
I
Line input dedicated load
I
Test pin (GND input)
I
Title-killer SW (1 = On, 0 = Off)
I
State data-setting data input
I
State data-setting clock
I
State data-latch pulse
O AWB, AE, and AF detection-data output
O Iris detection-area-setting pulse:
SP-A7 [8] output changeover
O Iris detection-area-setting pulse:
SP-A7 [8] output changeover
O Burst flag output
I
External CSYNC input
O Microprocessor clock output
(1/2 or 1/4 dividing of X’tal 1)
— 3.3 V power supply
— GND
O Vertical synchronization pulse
O Horizontal synchronization pulse
O Blanking pulse
O SYNC pulse
O Subcarrier blanking pulse (SECAM)
O Horizontal SYNC pulse (SECAM)
O SECAM determination pulse
O SECAM determination pulse
— 3.3 V power supply
— GND
I
2fsc oscillator input
O 2fsc oscillator output
I
Line-determination-signal input
I
Pin 13 MCK dividing setting SW
(1 = 1/2, 0 = 1/4)
I
Reset: to restore the initial data settings
O PLL signal output
O PLL signal output
I
Vertical synchronization signal input
I
4fsc oscillator input
O 4fsc oscillator output
O fsc output
— GND
— Analog system power supply: 3.3 V
— GND
— Analog system power supply: 3.3 V
— GND
O Chrominance-signal analog output
I
D/A upper current source
I
D/A lower current source
I
Reference voltage input
I/O
Format
ZC2R
ICS
IC
ICD
IC
ICS
ICS
ZC2R
ICZC2R
ICZC2R
ICZC2R
ICSD
OC2R
VCCI
GNDI
ICZC2R
ICZC2R
ICZC2R
ICZC2R
ICZC2R
OC2R
OC2R
ICZC2R
VCCC
GNDC
IQ3
OQ3
ICD
IC
ICS
ZC2
ZC2
ICSD
IQ2
OQ2
ICZC2R
GNDA
VCCA
GNDA
VCCA
GNDA
OA
IA
IA
IA
Rev.1.00 Jun 15, 2005 page 4 of 21