HD49815TF Datasheet, PDF (15/22 Pages) Hitachi Semiconductor – Digital Camera Signal Processor

HD49815TF
d. Y setup
Since the OB clamp processes the signal, the black level of the 10-bit signal input to the HD49815TF is fixed to
48/1024. The Y-setup circuit subtracts 48 at the black level. However, when 48 at the black level differs due to
the noise mixed in the analog signal, the Y-setup circuit subtracts that value.
The Y-setup circuit is set in State Data SP_A5 [6].
e. Gamma correction
The gamma-correction circuit implements the gamma-correction processing for the separated Y signal. Four
kinds of values can be set independently, according to the input-signal level, to acquire optimal gamma
characteristics: the gamma input limit, the gamma knee coefficient, the gamma coefficient, and the gamma black
clipping.
The gamma correction circuit is set in State Data SP_A5 [1 to 4].
f. Highlight enhancer
For input-Y signal levels in excess of 100 IRE, the highlight enhancer implements highlight enhancer processing.
This circuit is set in State Data SP_A5 [0, 5, and 14].
g. Fade
The fade circuit amplifies the luminance signal by a factor of 0 to 1.
This circuit is set in State Data SP_A5 [9].
4. Zoom, encode block, TG, SSG, and AWB and AE detection blocks
a. Zoom processing
The Y, R-Y, and B-Y signals completed the color-signal processing and the luminance-signal processing can be
electronically zoomed by a factor of 1 to 256.
After clipping CCD signals for V direction, zoom circuit clips these signals for H direction, and expand these
signals for H and V directions.
The zooming times and the read starting position for the V and H directions are set in State Data TM_A2 [3, 4, 5,
6, 8, and 9] and ZM_A0 to 6.
b. Encode block
This circuit encodes the signals completed the color-signal processing, the luminance-signal processing, and the
zoom processing as the NTSC/PAL TV-monitor method.
A DAC that converts the digital signal to an analog signal is provided. The DAC has two channels: one for R-Y
signals and one for B-Y signals.
c. TG and SSG
The TG generates the signals required to drive the CCD sensor (H1, H2, RG, SG1/2, and the V transfer pulse),
and the CDS/AGC control signals (SP1 and SP2).
In addition, the SSG generates the signals to synchronize with the TV monitor (the Sync signal).
The drive timing of the generated signals differs according to the manufacturer and the specifications of the
CCD sensor. Setting the state data enables setting of any timing.
The state data of TG and SSG can be set in TM_A0, A1, A2, A3, and A8.
d. AWB- and AE-detection blocks
The HD49815TF provides automatic white-balance (AWB) and automatic-iris (AE) detection circuits that are
indispensable for a camera.
The AWB-detection block takes the R-Y and B-Y color-difference signals completed the color-signal processing,
and converts to the R-B and MG-G axes. The converted signals are sent to circuits for the white detection to
obtain white signal components only, and the white-color difference value is detected. The 8-bit single-chip
microcomputer acquires this detection data, and controls the R and B gains to produce the true white.
The State Data of the AWB detection is AWB_A0 and A8.
The AE-detection block divides the CCD output signal converted to digital by the 10-bit ADC to six arbitrary
areas, and performs integration processing. This function enables detection of the lighting level of the image
signal.
The 8-bit single-chip microcomputer acquires this detection data, and controls the accumulation amount (the
shutter) of the CCD sensor or the iris motor of the lens to maintain the proper lighting.
The State Data of the AF detection is AE_A0 to A7 and A8.
Rev.1.00 Jun 15, 2005 page 15 of 21