H8S18 Datasheet, PDF (389/758 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2200 Series

Section 9 16-Bit Timer Pulse Unit (TPU)
Contention between TGR Write and Compare Match: If a compare match occurs in the T₂
state of a TGR write cycle, the TGR write takes precedence and the compare match signal is
inhibited. A compare match does not occur even if the same value as before is written. Figure 9.47
shows the timing in this case.
φ
Address
Write signal
Compare
match signal
TCNT
TGR write cycle
T₁
T₂
TGR address
Prohibited
N
N+1
TGR
N
M
TGR write data
Figure 9.47 Contention between TGR Write and Compare Match
Rev.7.00 Dec. 24, 2008 Page 333 of 698
REJ09B0074-0700