H8S18 Datasheet, PDF (164/758 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2200 Series

Section 5 Interrupt Controller
5.6.4 Interrupt Response Times
Table 5.4 shows interrupt response times ⎯ the interval between generation of an interrupt request
and execution of the first instruction in the interrupt handling routine. The execution status
symbols used in table 5.4 are explained in table 5.5.
This LSI is capable of fast word transfer to on-chip memory, and have the program area in on-chip
ROM and the stack area in on-chip RAM, enabling high-speed processing.
Table 5.4 Interrupt Response Times
Normal Mode*⁵
Advanced Mode
No. Execution State
1
Interrupt priority determination*¹
Interrupt
Control
Mode 0
3
Interrupt
Control
Mode 2
3
Interrupt
Control
Mode 0
3
Interrupt
Control
Mode 2
3
2
Number of wait states until
executing instruction ends*²
3
PC, CCR, EXR stack save
4
Vector fetch
5
Instruction fetch*³
6
Internal processing*⁴
1 to 19+2·S_I 1 to 19+2·S_I 1 to 19+2·S_I 1 to 19+2·S_I
2·S_K
S_I
2·S_I
2
3·S_K
S_I
2·S_I
2
2·S_K
2·S_I
2·S_I
2
3·S_K
2·S_I
2·S_I
2
Total (using on-chip memory)
11 to 31
12 to 32
12 to 32
13 to 33
Notes: 1. Two states in case of internal interrupt.
2. Refers to MULXS and DIVXS instructions.
3. Prefetch after interrupt acceptance and interrupt handling routine prefetch.
4. Internal processing after interrupt acceptance and internal processing after vector fetch.
5. Not available in this LSI.
Rev.7.00 Dec. 24, 2008 Page 108 of 698
REJ09B0074-0700