H8S18 Datasheet, PDF (234/758 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2200 Series

Section 7 DMA Controller (DMAC)
7.4.2 Sequential Mode
Sequential mode can be specified by clearing the RPE bit in DMACR to 0. In sequential mode,
MAR is updated after each byte or word transfer in response to a single transfer request, and this is
executed the number of times specified in ETCR. One address is specified by MAR, and the other
by IOAR. The transfer direction can be specified by the DTDIR bit in DMACR. Table 7.3
summarizes register functions in sequential mode.
Table 7.3 Register Functions in Sequential Mode
Register
23
MAR
23
15
H'FF
IOAR
15
0
ETCR
Function
DTDIR = 0 DTDIR = 1
0 _Source
address
register
Destination
address
register
0 _Destination
address
register
Source
address
register
Transfer counter
Initial Setting
Operation
Start address of
Incremented/
transfer destination decremented every
or transfer source transfer
Start address of
Fixed
transfer source or
transfer destination
Number of transfers Decremented every
transfer, transfer
ends when count
reaches H'0000
MAR specifies the start address of the transfer source or transfer destination as 24 bits. MAR is
incremented or decremented by 1 or 2 each time a byte or word is transferred. IOAR specifies the
lower 16 bits of the other address. The 8 bits above IOAR have a value of H'FF. Figure 7.2
illustrates operation in sequential mode.
Rev.7.00 Dec. 24, 2008 Page 178 of 698
REJ09B0074-0700