H8S2456 Datasheet, PDF (388/1376 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer H8S Family / H8S/2400 Series

Section 7 DMA Controller (DMAC)
Address T_A
1st block
2nd block
Transfer
Consecutive transfer
of M bytes or words
is performed in
response to one
request
Block area
Address T_B
Address B_B
Address B_A
Nth block
Legend:
Address TA = LA
Address TB = LB
Address BA = LA + SAIDE · (–1)^SAID · (2^DTSZ · (M·N – 1))
Address BB = LB + DAIDE · (–1)^DAID · (2^DTSZ · (N – 1))
Where : LA = Value set in MARA
LB = Value set in MARB
N = Value set in ETCRB
M = Value set in ETCRAH and ETCRAL
Figure 7.13 Operation in Block Transfer Mode (BLKDIR = 0)
Figure 7.14 illustrates operation in block transfer mode when MARA is designated as a block area.
Rev. 1.00 Sep. 19, 2008 Page 358 of 1342
REJ09B0467-0100