H8S2456 Datasheet, PDF (257/1376 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer H8S Family / H8S/2400 Series

Section 6 Bus Controller (BSC)
6.7.9 Wait Control
There are two ways of inserting wait states in a DRAM access cycle: program wait insertion and
pin wait insertion using the WAIT pin.
Wait states are inserted to extend the CAS assertion period in a read access to DRAM space, and
to extend the write data setup time relative to the falling edge of CAS in a write access.
(1) Program Wait Insertion
When the bit in ASTCR corresponding to an area designated as DRAM space is set to 1, from 0 to
7 wait states can be inserted automatically between the T_c1 state and T_c2 state, according to the
settings in WTCR.
(2) Pin Wait Insertion
When the WAITE bit in BCR is set to 1 and the ASTCR bit is set to 1, wait input by means of the
WAIT pin is enabled. When DRAM space is accessed in this state, a program wait (T_w) is first
inserted. If the WAIT pin is low at the falling edge of φ in the last T_c1 or T_w state, another T_w state
is inserted. If the WAIT pin is held low, T_w states are inserted until it goes high.
Figures 6.38 and 6.39 show examples of wait cycle insertion timing in the case of 2-state and 3-
state column address output cycles.
Rev. 1.00 Sep. 19, 2008 Page 227 of 1342
REJ09B0467-0100