H8S2456 Datasheet, PDF (103/1376 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer H8S Family / H8S/2400 Series

Section 2 CPU
In normal mode the memory operand is a word operand and the branch address is 16 bits long. In
advanced mode the memory operand is a longword operand, the first byte of which is assumed to
be all 0 (H'00). Note that the first part of the address range is also the exception vector area. For
further details, see section 4, Exception Handling.
If an odd address is specified in word or longword memory access, or as a branch address, the
least significant bit is regarded as 0, causing data to be accessed or instruction code to be fetched
at the address preceding the specified address. (For further information, see section 2.5.2, Memory
Data Formats.)
Note: Normal mode is not available in this LSI.
Specified
by @aa:8
Branch address
Specified
by @aa:8
Reserved
Branch address
(a) Normal Mode*
(a) Advanced Mode
Note: * Normal mode is not available in this LSI.
Figure 2.12 Branch Address Specification in Memory Indirect Mode
Rev. 1.00 Sep. 19, 2008 Page 73 of 1342
REJ09B0467-0100