H8S2456 Datasheet, PDF (1184/1376 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer H8S Family / H8S/2400 Series

Section 24 Clock Pulse Generator
24.1 Register Descriptions
The clock pulse generator has the following registers.
• System clock control register (SCKCR)
• PLL control register (PLLCR)
• USB PLL control register (USPLLCR)
24.1.1 System Clock Control Register (SCKCR)
SCKCR controls φ clock output and selects operation when the PLLCR register setting is changed.
Bit Bit Name Initial Value R/W
7
PSTOP
0
R/W
6
—
0
R/W
Description
φ Clock Output Disable
Controls φ output.
Normal Operation
0: φ output
1: Fixed high
Sleep Mode
0: φ output
1: Fixed high
Software Standby Mode
0: Fixed high
1: Fixed high
Hardware Standby Mode
0: High impedance
1: High impedance
All module clock stop mode
0: φ output
1: Fixed high
Reserved
This bit can be read from or written to. However,
the write value should always be 0.
Rev. 1.00 Sep. 19, 2008 Page 1154 of 1342
REJ09B0467-0100