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M32C84 Datasheet, PDF (361/529 Pages) Renesas Technology Corp – 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES
M32C/84 Group (M32C/84, M32C/84T)
23.1.12 CAN0 Slot Interrupt Mask Register (C0SIMKR Register)
23. CAN Module
CAN0 Slot Interrupt Mask Register(1)
b15
b8 b7
b0
Symbol
C0SIMKR
Address
021116 - 021016
After Reset(2)
000016
Bit
Symbol
Bit Name
Slot 15 Interrupt
SIM15 Request Mask Bit
Slot 14 Interrupt
SIM14 Request Mask Bit
Slot 13 Interrupt
SIM13 Request Mask Bit
Slot 12 Interrupt
SIM12 Request Mask Bit
Slot 11 Interrupt
SIM11 Request Mask Bit
Slot 10 Interrupt
SIM10 Request Mask Bit
Slot 9 Interrupt
SIM9 Request Mask Bit
Slot 8 Interrupt
SIM8 Request Mask Bit
Function
RW
Controls whether the interrupt
RW
request of the corresponding
message slot is enabled or masked.
RW
0: Masks (disables) an interrupt request
1: Enables an interrupt request
RW
RW
RW
RW
RW
RW
Slot 7 Interrupt
SIM7 Request Mask Bit
RW
Slot 6 Interrupt
SIM6 Request Mask Bit
RW
Slot 5 Interrupt
SIM5 Request Mask Bit
RW
Slot 4 Interrupt
SIM4 Request Mask Bit
RW
Slot 3 Interrupt
SIM3 Request Mask Bit
RW
Slot 2 Interrupt
SIM2 Request Mask Bit
RW
Slot 1 Interrupt
SIM1 Request Mask Bit
RW
Slot 0 Interrupt
SIM0 Request Mask Bit
RW
NOTES:
1. Change the C0SIMKR register setting while the C0MCTLj (j=0to 15) register, corresponding to the bit
to be changed, is set to "0016".
2. Value is obtained by setting the SLEEP bit in the C0SLPR register to "1" (sleep mode exited) after
reset and supplying the clock to the CAN module.
Figure 23.14 C0SIMKR Register
The C0SIMKR register determines whether an interrupt request, generated by a data transmission or
reception in the corresponding message slot is enabled or disabled. When the SIMj bit (j=0 to 15) is set
to "1" (no interrupt requested), an interrupt request generated by a data transmission or reception in the
corresponding message slot is enabled. Refer to 23.4 CAN Interrupt for details.
Rev. 1.01 Jul. 07, 2005 Page 340 of 495
REJ09B0036-0101