M32C84 Datasheet, PDF (115/529 Pages) Renesas Technology Corp – 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES

M32C/84 Group (M32C/84, M32C/84T)
9. Clock Generation Circuit
9.1.4 PLL Clock
The PLL frequency synthesizer generates the PLL clock based on the main clock. The PLL clock can be
used as clock source for the CPU clock and peripheral function clock.
The PLL frequency synthesizer stops after reset. When the PLC07 bit is set to "1" (PLL on), the PLL
frequency synthesizer starts operating. Wait tsu(PLL) ms for the PLL clock to stabilize.
The PLL clock can either be the clock output from the voltage controlled oscillator (VCO) divided-by-2 or
divided-by-3. When the PLL clock is used as a clock source for the CPU clock or peripheral function
clock, set each bit as is shown in Table 9.3. Figure 9.12 shows the procedure to use the PLL clock as the
CPU clock source.
To enter wait or stop mode, set the CM17 bit to "0" (main clock as CPU clock source), set the PLC07 bit
in the PLC0 register to "0" (PLL off) and then enter wait or stop mode.
Table 9.3 Bit Settings to Use PLL Clock as CPU Clock Source
f(XIN)
PLC0 Register
PLC1 Register
PLL Clock
PLC02 Bit PLC01 Bit PLC00 Bit CM21 Bit
10 MHz
0
1
1
0
30 MHz
1
20 MHz
8 MHz
1
0
0
0
32 MHz
1
21.3 MHz
Use PLL clock as CPU clock source
Set the PLC0 and the PLC1 registers
(Set the PLC07 bit to "0")
Set the PLC07 bit to "1"
(PLL on)
Wait tsu(PLL)ms
Set the CM17 bit to "1"
(PLL clock as CPU clock source)
End
PLC07 bit : Bit in the PLC0 Register
CM17 bit : Bit in the CM1 Register
Figure 9.12 Procedure to Use PLL Clock as CPU Clock Source
Rev. 1.01 Jul. 07, 2005 Page 94 of 495
REJ09B0036-0101