M32C84 Datasheet, PDF (116/529 Pages) Renesas Technology Corp – 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES

M32C/84 Group (M32C/84, M32C/84T)
9. Clock Generation Circuit
9.2 CPU Clock and BCLK
The CPU operating clock is referred to as the CPU clock. The CPU clock is also a count source for the
watchdog timer. After reset, the CPU clock is the main clock divided-by-8 . In memory expansion or micro-
processor mode, the clock having the same frequency as the CPU clock can be output from the BCLK pin
as BCLK. Refer to 9.4 Clock Output Function for details.
The main clock, sub clock, on-chip oscillator clock or PLL clock can be selected as a clock source for the
CPU clock. Table 9.4 shows CPU clock source and bit settings.
When the main clock, on-chip oscillator clock or PLL clock is selected as a clock source of the CPU clock,
the selected clock divided-by-1 (no division), -2, -3, -4, -6, -8, -10, -12, -14 or -16 becomes the CPU clock.
The MCD4 to MCD0 bits in the MCD register select the clock division.
When the microcomputer enters stop mode or low-power consumption mode (except when the on-chip
oscillator clock is the CPU clock), the MCD4 to MCD0 bits are set to "010002" (divide-by-8 mode). There-
fore, when the main clock starts running, the CPU clock enters medium-speed mode (divide-by-8).
Table 9.4 CPU Clock Source and Bit Settings
CPU Clock Source
CM0 Register CM1 Register CM2 Register PM2 Register
CM07 Bit
CM17 Bit
CM21 Bit
PM24 Bit
Main Clock
Main Clock (Main Clock Direct Mode)⁽¹⁾
0
0
0
0
0
0
0
1
Sub Clock
1
0
0
0
On-Chip Oscillator Clock
0
0
1
0
PLL Clock
0
1
0
0
NOTES:
1. Refer to 23.2 CAN Clock for details.
9.3 Peripheral Function Clock
The peripheral function clock becomes an operating clock or count source for peripheral functions exclud-
ing the watchdog timer.
9.3.1 f1, f8, f32 and f2n
f1, f8 and f32 are the peripheral function clock, selected by the CM21 bit, divided-by-1, -8, or -32. The
PM27 and PM26 bits in the PM2 register selects a f2n count source from the peripheral clock, XIN clock,
and the on-chip oscillator clock. The CNT3 to CNT0 bits in the TCSPR register selects a f2n division. (n=1
to 15. No division when n=0.)
f1, f8, f32 and f2n stop when the CM02 bit in the CM0 register to "1" (peripheral function stops in wait mode)
to enter wait mode or when in low-power consumption mode.
f1, f8 and f2n are used as an operating clock of the serial I/O and count source of the timers A and B. f1 is
also used as an operating clock for the intelligent I/O.
The CLKOUT pin outputs f8 and f32 . Refer to 9.4 Clock Output Function for details.
9.3.2 fAD
fAD is an operating clock for the A/D converter and has the same frequency as either the main clock⁽¹⁾ or
the on-chip oscillator clock. The CM21 bit determines which clock is selected.
If the CM02 bit is set to "1" (peripheral function stop in wait mode) to enter wait mode, fAD stops. fAD also
stops in low-power consumption mode.
NOTES:
1. The PLL clock, instead of the main clock, when the CM17 bit is set to "1" (PLL clock).
Rev. 1.01 Jul. 07, 2005 Page 95 of 495
REJ09B0036-0101