PD78F0701Y_15 Datasheet, PDF (36/54 Pages) Renesas Technology Corp – 8-BIT SINGLE-CHIP MICROCONTROLLER

µPD78F0701Y
(e) UART mode (dedicated baud rate generator output)
Parameter
Symbol
Conditions
Transfer rate
MIN.
TYP.
MAX.
Unit
38,836
bps
(f) UART mode (external clock input)
Parameter
Symbol
Conditions
ASCK0 cycle time
ASCK0 high/low
level width
Transfer rate
tKCY3
tKH3, tKL3
MIN.
800
400
TYP.
MAX.
Unit
ns
ns
39,063
bps
(g) I²C bus mode
Parameter
Symbol
SCL0 clock frequency
Bus free time (between stop-start
conditions)
Note 1
Hold time
SCL0 clock low level width
SCL0 clock high level width
Start/restart condition setup time
Data
CBUS-compatible master
hold time _I2_{C bus}
Data setup time
SDA0 and SCL0 signal rising time
SDA0 and SCL0 signal falling time
Stop condition setup time
Pulse width of spikes controlled by the
input filter
Capacitive load of each bus line
fSCL
tBUF
tHD:STA
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tR
tF
tSU:STO
tSP
Cb
Standard mode
MIN.
MAX.
0
100
4.7
-
4.0
4.7
4.0
4.7
5.0
Note 2
0
250
-
-
4.0
-
-
-
-
-
-
-
-
1,000
300
-
-
-
400
High-speed mode
Unit
MIN.
MAX.
0
400
kHz
1.3
-
µs
0.6
-
µs
1.3
-
µs
0.6
-
µs
0.6
-
µs
-
-
µs
Note 2
0
Note 3
0.9
µs
Note 4
100
-
ns
-
300
ns
-
300
ns
0.6
-
µs
0
50
ns
-
400
pF
Notes 1. In the start condition, the first clock pulse is generated after this period of time.
2. To fill the undefined area of the SCL0 falling edge (at VIHmin. of the SCL0 signal), the device needs to
internally provide a hold time of at least 300 ns for the SDA0 signal.
3. If the device does not extend the low hold time (tLOW) of the SCL0 signal, the maximum data hold time
(tHD:DAT) only needs to be satisfied.
4. High-speed mode I²C bus can be used in standard mode I²C bus system. In this case, the following
conditions must be satisfied:
• When the device does not extend the low hold time of the SCL0 signal
tSU:DAT ≥ 250 ns
• When the device extends the low hold time of the SCL0 signal
Before SCL0 is released (tRmax. + tSU:DAT = 1,000 + 250 = 1,250 ns: for standard mode I²C bus
system), the next data bit must be sent onto the SDA0 line.
34
Preliminary Product Information U13563EJ2V0PM00