H8S2639 Datasheet, PDF (346/1547 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 9 I/O Ports
Pin PF0 is setting a PFDDR bit to 1 makes the corresponding port F pin an output port, while
clearing the bit to 0 makes the pin an input port.
• Mode 7
Setting a PFDDR bit to 1 makes the corresponding port F pin PF6 to PF3, PF0 an output port,
or in the case of pin PF7, the φ output pin. Clearing the bit to 0 makes the pin an input port.
Port F Data Register (PFDR)
Bit
:
Initial value :
R/W
:
7
PF7DR
0
R/W
6
PF6DR
0
R/W
5
PF5DR
0
R/W
4
PF4DR
0
R/W
3
2
1
0
PF3DR —
— PF0DR
0
undefined undefined
0
R/W
—
—
R/W
PFDR is an 8-bit readable/writable register that stores output data for the port F pins (PF7 to PF3,
PF0).
PFDR is initialized to B'00000**0 by a reset, and in hardware standby mode. It retains its prior
state in software standby mode.
Port F Register (PORTF)
Bit
:7
6
5
4
PF7
PF6
PF5
PF4
Initial value : —^*
—^*
—^*
—^*
R/W
:R
R
R
R
Note: * Determined by state of pins PF7 to PF3, PF0.
3
2
1
0
PF3
—
—
PF0
—^* undefined undefined —^*
R
—
—
R
PORTF is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of
output data for the port F pins (PF7 to PF3, PF0) must always be performed on PFDR.
If a port F read is performed while PFDDR bits are set to 1, the PFDR values are read. If a port F
read is performed while PFDDR bits are cleared to 0, the pin states are read.
After a reset and in hardware standby mode, PORTF contents are determined by the pin states, as
PFDDR and PFDR are initialized. PORTF retains its prior state in software standby mode.
Rev. 6.00 Feb 22, 2005 page 286 of 1484
REJ09B0103-0600