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| H8S2639 Datasheet, PDF (22/1547 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series | |||
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Item
23B.1 Overview
Page
973
974
Table 23B-2 LSI
976
Internal States in Each
Mode (H8S/2639
Group, H8S/2635
Group)
23.2.3 Low-Power 983
Control Register
(LPWRCR)
23.2.4 Timer
985
Control/Status Register
(TCSR)
986
Revision (See Manual for Details)
Description amended
... The chip operating modes are as follows: (3) Subactive
mode* (U-mask, W-mask version, H8S/2635 Group only) ... (5)
Subsleep mode* (U-mask, W-mask version, H8S/2635 Group
only) ... (6) Watch mode* (U-mask, W-mask version, H8S/2635
Group only) ...
Note * amended
Note: * Subclock functions (subactive mode, subsleep mode,
and watch mode) are available in the U-mask and W-mask
versions, and H8S/2635 Group only. ...
Note *3 added
DTC*3 PBC*3 PPG*3 D/A0, 1*3
Note: 3. The DTC, PBC, PPB, DA0, and DA1 are not
implemented in the H8S/2635 and H8S/2634.
Note * amended
Note: * Bits 7 to 3 in LPWRCR are valid in the U-mask and W-
mask versions, and H8S/2635 Group; they are reserved bits in
all other versions. â¦
Note * amended
Note: 2. Bit 4 (PSS) in TCSR of WDT1 is valid in the U-mask
and W-mask versions, and H8S/2635 Group. In versions other
than the U-mask and W-mask versions, and H8S/2635 Group,
however, the PSS bit ...
Bit 4Prescaler Select (PSS)
Note 2 amended
Note: 2. Bit 4 (PSS) in TCSR of WDT1 is valid in the U-mask
and W-mask versions, and H8S/2635 Group. In versions other
than the U-mask and W-mask versions, and H8S/2635 Group,
however, the PSS bit ...
Rev. 6.00 Feb 22, 2005 page xxii of lx
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