H8S2639 Datasheet, PDF (1216/1547 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Appendix A Instruction Set
A.6 Condition Code Modification
This section indicates the effect of each CPU instruction on the condition code. The notation used
in the table is defined below.
m = 31 for longword operands
15 for word operands
7 for byte operands
Si
The i-th bit of the source operand
Di
The i-th bit of the destination operand
Ri
The i-th bit of the result
Dn The specified bit in the destination operand
—
Not affected
Modified according to the result of the instruction (see definition)
0
Always cleared to 0
1
Always set to 1
*
Undetermined (no guaranteed value)
Z'
Z flag before instruction execution
C'
C flag before instruction execution
Rev. 6.00 Feb 22, 2005 page 1156 of 1484
REJ09B0103-0600