H8S2639 Datasheet, PDF (1435/1547 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Appendix B Internal I/O Register
TCR5—Timer Control Register 5
H'FEA0
TPU5
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
0
¾ CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0
0
0
0
0
0
0
0
0
¾
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Time Prescaler
0 0 0 Internal clock: counts on f/1
1 Internal clock: counts on f/4
1 0 Internal clock: counts on f/16
1 Internal clock: counts on f/64
1 0 0 External clock: counts on TCLKA pin input
1 External clock: counts on TCLKC pin input
1 0 Internal clock: counts on f/256
1 External clock: counts on TCLKD pin input
Note: This setting is ignored when channel 5 is in phase
counting mode.
Clock Edge
0 0 Count at rising edge
1 Count at falling edge
1
Count at both edges
Note: This setting is ignored when channel 5 is in phase
counting mode.
Internal clock edge selection is valid when the input
clock is f/4 or slower. This setting is ignored if the
input clock is f/1, or when overflow/underflow of
another channel is selected.
Counter Clear
0 0 TCNT clearing disabled
1 TCNT cleared by TGRA compare match/input capture
1 0 TCNT cleared by TGRB compare match/input capture
1 TCNT cleared by counter clearing for another channel
performing synchronous clearing/synchronous operation*
Note: * Synchronous operation setting is performed by setting the
SYNC bit in TSYR to 1.
Rev. 6.00 Feb 22, 2005 page 1375 of 1484
REJ09B0103-0600