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| NP30N04QUK_15 Datasheet, PDF (3/9 Pages) Renesas Technology Corp – 40 V – 30 A – Dual N-channel Power MOS FET Application: Automotive | |||
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NP30N04QUK
Electrical Characteristics (TA = 25°C)
Item
Symbol Min
Zero Gate Voltage Drain Current IDSS
Gate Leakage Current
IGSS
Gate to Source Threshold Voltage VGS(th)
2
Forward Transfer Admittance â1
| yfs |
13
Drain to Source On-state
Resistance â1
RDS(on)
Input Capacitance
Ciss
Output Capacitance
Coss
Reverse Transfer Capacitance
Crss
Turn-on Delay Time
td(on)
Rise Time
tr
Turn-off Delay Time
td(off)
Fall Time
tf
Total Gate Charge
QG
Gate to Source Charge
QGS
Gate to Drain Charge
Body Diode Forward Voltage â1
QGD
VF(S-D)
Reverse Recovery Time
trr
Reverse Recovery Charge
Qrr
Note: *1. Pulsed test
Typ
3
26
6.5
1600
220
90
20
8
47
6
27
9
6
0.9
32
35
Max
1
±100
4
8
2400
330
160
40
20
94
15
41
1.5
Unit
μA
nA
V
S
mΩ
Test Conditions
VDS = 40 V, VGS = 0 V
VGS = ±20 V, VDS = 0 V
VDS = VGS, ID = 250 μA
VDS = 5 V, ID = 15 A
VGS = 10 V, ID = 15 A
pF VDS = 25 V,
pF
VGS = 0 V,
pF f = 1 MHz
ns VDD = 20 V, ID = 15 A,
ns
VGS = 10 V,
ns
RG = 0 Ω
ns
nC VDD = 32 V,
nC VGS = 10 V,
nC ID = 30 A
V
IF = 30 A, VGS = 0 V
ns
IF = 30 A, VGS = 0 V,
nC di/dt = 100 A/μs
TEST CIRCUIT 1 AVALANCHE CAPABILITY
D.U.T.
RG = 25 Ω
L
PG.
VGS = 20 â 0 V
50 Ω
VDD
BVDSS
ID IAS
VDD
VDS
Starting Tch
TEST CIRCUIT 3 GATE CHARGE
D.U.T.
IG = 2 mA
RL
PG.
50 Ω
VDD
TEST CIRCUIT 2 SWITCHING TIME
D.U.T.
PG.
RG
VGS
0
Ï
Ï = 1 μs
Duty Cycle ⤠1%
RL
VGS
VGS
Wave Form
10%
0
VDD
VDS
90%
VDS
VDS
0
Wave Form
td(on)
90%
VGS
90%
10% 10%
tr td(off)
tf
ton
toff
R07DS1227EJ0100 Rev.1.00
Nov 18, 2014
Page 3 of 7
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