UPD78F9202MA-CAC-A Datasheet, PDF (242/342 Pages) Renesas Technology Corp – 8-Bit Single-Chip Microcontrollers

CHAPTER 16 FLASH MEMORY
Figure 16-12. Format of Flash Status Register (PFS)
Address: FFA1H
Symbol
7
PFS
0
After reset: 00H
6
5
0
0
R/W
4
0
3
2
1
0
0
WEPRERR VCERR FPRERR
1. Operating conditions of FPRERR flag
<Setting conditions>
• If PFCMD is written when the store instruction operation recently performed on a peripheral register is not to
write a specific value (A5H) to FLPMC
• If the first store instruction operation after <1> is on a peripheral register other than FLPMC
• If the first store instruction operation after <2> is on a peripheral register other than FLPMC
• If a value other than the inverted value of the value to be set to FLPMC is written by the first store instruction
after <2>
• If the first store instruction operation after <3> is on a peripheral register other than FLPMC
• If a value other than the value to be set to FLPMC (value written in <2>) is written by the first store instruction
after <3>
Remark The numbers in angle brackets above correspond to the those in (2) Flash protect command
register (PFCMD).
<Reset conditions>
• If 0 is written to the FPRERR flag
• If the reset signal is generation
2. Operating conditions of VCERR flag
<Setting conditions>
• Erasure verification error
• Internal writing verification error
If VCERR is set, it means that the flash memory has not been erased or written correctly. Erase or write the
memory again in the specified procedure.
Remark The VCERR flag may also be set if an erase or write protect error occurs.
<Reset conditions>
• When 0 is written to the VCERR flag
• When the reset signal generation
3. Operating conditions of WEPRERR flag
<Setting conditions>
• If the area specified by the protect byte to be protected from erasing or writing is specified by the flash
address pointer H (FLAPH) and a command is executed to this area
• If 1 is written to a bit that has not been erased (a bit for which the data is 0).
<Reset conditions>
• When 0 is written to the WEPRERR flag
• When the reset signal generation
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User’s Manual U18172EJ3V0UD