UPD78F9202MA-CAC-A Datasheet, PDF (158/342 Pages) Renesas Technology Corp – 8-Bit Single-Chip Microcontrollers

CHAPTER 8 WATCHDOG TIMER
(2) When the watchdog timer operation clock is the low-speed internal oscillation clock (fRL) when the STOP
instruction is executed
When the STOP instruction is executed, operation of the watchdog timer is stopped. After STOP mode is
released, operation stops for 34 μs (TYP.) and then counting is started again using the operation clock before the
operation was stopped. At this time, the counter is not cleared to 0 but holds its value.
Figure 8-7. Operation in STOP Mode (WDT Operation Clock: Low-Speed Internal Oscillation Clock)
<R>
<1> CPU clock: Crystal/ceramic oscillation clock (μPD78F920x Only)
Normal
CPU operation operation
fCPU
fRL
Watchdog timer
Operating
STOP
Operation
stopped^Note
Oscillation stabilization time
Oscillation stopped
Oscillation stabilization time
(set by OSTS register)
Operation stopped
Operating
Normal operation
<2> CPU clock: High-speed internal oscillation clock or external clock input
Normal
CPU operation ^operation
fCPU
fRL
Watchdog timer
Operating
STOP
Operation
stopped^Note
Oscillation stopped
Operation stopped
Normal operation
Operating
Note The operation stop time is 17 μs (MIN.), 34 μs (TYP.), and 67 μs (MAX.).
8.4.4 Watchdog timer operation in HALT mode (when “low-speed internal oscillator can be stopped by
software” is selected by option byte)
The watchdog timer stops counting during HALT instruction execution regardless of whether the operation clock of
the watchdog timer is the system clock (fX) or low-speed internal oscillation clock (fRL). After HALT mode is released,
counting is started again using the operation clock before the operation was stopped. At this time, the counter is not
cleared to 0 but holds its value.
Figure 8-8. Operation in HALT Mode
CPU operation Normal operation
fCPU
HALT
Normal operation
fX or fRL
Watchdog timer
Operating Operation stopped
Operating
156
User’s Manual U18172EJ3V0UD