PD46364092B Datasheet, PDF (24/36 Pages) Renesas Technology Corp – 36M-BIT DDR II SRAM 2-WORD BURST OPERATION

μPD46364092B, μPD46364182B, μPD46364362B
JTAG AC Characteristics (TA = 0 to 70°C)
Parameter
Clock
Clock cycle time
Clock frequency
Clock HIGH time
Clock LOW time
Symbol
t_THTH
f_TF
t_THTL
t_TLTH
Conditions
Output time
TCK LOW to TDO unknown
TCK LOW to TDO valid
t_TLOX
t_TLOV
Setup time
TMS setup time
TDI valid to TCK HIGH
Capture setup time
t_MVTH
t_DVTH
t_CS
Hold time
TMS hold time
TCK HIGH to TDI invalid
Capture hold time
t_THMX
t_THDX
t_CH
JTAG Timing Diagram
MIN.
50
20
20
0
5
5
5
5
5
5
MAX.
20
Unit
ns
MHz
ns
ns
ns
10
ns
ns
ns
ns
ns
ns
ns
TCK
TMS
TDI
TDO
tMVTH
tTHTH
tTHTL
tTLTH
tTHMX
tDVTH
tTHDX
tTLOX
tTLOV
R10DS0091EJ0400 Rev.4.00
Nov 09, 2012
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