PD46364092B Datasheet, PDF (20/36 Pages) Renesas Technology Corp – 36M-BIT DDR II SRAM 2-WORD BURST OPERATION

μPD46364092B, μPD46364182B, μPD46364362B
Read and Write Timing
NOP
READ
READ NOP
(burst of 2) (burst of 2)
NOP
WRITE WRITE READ
(burst of 2) (burst of 2) (burst of 2)
1
2
3
4
5
6
7
8
9
10
TKHKH
K
TKHKL TKLKH
TKHK#H TK#HKH
K#
LD#
R, W#
Address
DQ
CQ
CQ#
C
C#
TIVKH
TKHIX
TAVKH TKHAX
A0
A1
Qx2
TKHCH
TKHCH
TCHQX1
TCHQV
A2
A3
A4
TKHDX
TKHDX
TDVKH
Q00 Q01 Q10 Q11
TDVKH
D20 D21 D30 D31
TCHQX
TCHQV
TCHQZ
TCHQX
TCHCQX
TCHCQV
TCHCQX
TCHCQV
TCQHCQ#H TCQ#HCQH
Q40 Q41
TCQHQX
TCQHQV
TKHKL TKLKH TKHKH TKHK#H TK#HKH
Remarks 1. Q01 refers to output from address A0.
Q02 refers to output from the next internal burst address following A0, etc.
2. Outputs are disabled (high impedance) 2.5 clock cycles after the last READ (LD# = LOW, R, W# =
HIGH) is input in the sequences of [READ]-[NOP].
3. The second NOP cycle at the cycle “5” is not necessary for correct device operation;
however, at high clock frequencies it may be required to prevent bus contention.
R10DS0091EJ0400 Rev.4.00
Nov 09, 2012
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