PD46364092B Datasheet, PDF (12/36 Pages) Renesas Technology Corp – 36M-BIT DDR II SRAM 2-WORD BURST OPERATION

μPD46364092B, μPD46364182B, μPD46364362B
Bus Cycle State Diagram
LOAD NEW
ADDRESS
Count = 0
Load, Count = 2
Read
Load, Count = 2
Write
READ DOUBLE
Count = Count + 2
WRITE DOUBLE
Count = Count + 2
NOP,
Count = 2
Power UP
Supply voltage provided
NOP
NOP
NOP,
Count = 2
Load
Remarks 1. A0 is internally advanced in accordance with the burst order table.
Bus cycle is terminated after burst count = 2.
2. State machine control timing sequence is controlled by K.
R10DS0091EJ0400 Rev.4.00
Nov 09, 2012
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