7630_03 Datasheet, PDF (208/238 Pages) Renesas Technology Corp – 8-BIT SINGLE-CHIP MICROCOMPUTER

APPENDIX
3.5 List of registers
Watchdog timer register (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Watchdog timer register (WDT) [Address : 002E16]
B
Name
0 _{Not used (“1” when read.)}
1
2
3
4
5
Stop instruction disable bit
6
Function
At reset R W
1
1
1
1
1
1
0 : Stop instruction enabled
0
1 : Stop instruction disabled
Executed two NOP instructions
instead of STP instruction (Note 2)
7
Upper byte count source selection
bit
0 : Underflow of the low order counter
1 : φ divided by 256
0
Note 1: Writing to this register reloads the watchdog timer counters with the following initial
values irrespective of the value written. After reload, the watchdog timer counts down.
• The high-order counter WDH (7-bit counter) is set to “7F16”.
• The low-order counter WDL (4-bit counter) is set to “F16”.
The time-out period of the watchdog timer is n^V cycles of the internal system clock φ .
V • n = 524288 when the Upper byte count source selection bit is “0”.
• n = 32768 when the Upper byte count source selection bit is “1”.
On a watchdog timer underflow, the watchdog timer interrupt (non-maskable) occurs.
Set the watchdog timer counters to the default values prevent from underflow by writing
to this register in main processing.
Once the watchdog timer has been started, it cannot be stopped except by reset.
Note 2: Once the Stop instruction is disabled, it cannot be enabled again except by reset.
Fig. 3.5.31 Structure of Watchdog timer register
Polarity control register
b7 b6 b5 b4 b3 b2 b1 b0
Polarity control register (PCON) [Address : 002F16]
B
Name
0 ^{Key-on wake-up polarity}
control bit
Function
0: Low level active (P4 pull-up)
1: High level active (P4 pull-down)
At reset _{R W}
0
1 ^{CAN module dominant level}
control bit (Note)
0: Low level dominant (P32 pull-up)
0
1: High level dominant (P32 pull-down)
2
?
3
?
4 Not used (undefined when read.)
?
5
?
6
?
7
?
Note: The selected dominant level also controls the polarity of the pull-transistor enabled
by the P32 pull-up/down transistor control bit (bit 2 of the Port P3 pull-up control
register), the transistor pulling toward the recessive level is selected.
Fig. 3.5.32 Structure of Polarity control register
7630 Group User’s Manual
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