7630_03 Datasheet, PDF (176/238 Pages) Renesas Technology Corp – 8-BIT SINGLE-CHIP MICROCOMPUTER

APPENDIX
3.1 Electrical characteristics
3.1.4 A-D converter characteristics
Table 3.1.4 A-D converter characteristics
(Vcc = 4.0V to 5.5V, Vss = AVss = 0V, Ta = –40°C to 85°C, unless otherwise noted)
Symbol
Parameter
Test conditions
Limits
Unit
Min.
Typ.
Max.
–
Resolution
8
Bits
–
Absolute accuracy
±1
±2.5 LSB
tCONV
Conversion time
High- speed mode
106
108
tc(XIN)
Middle-speed mode
424
432
tc(XIN)
VREF
Reference input voltage
2.0
VCC
V
IREF
Reference input current
VCC = VREF = 5.12V
150
200
µA
RLADDER
Ladder resistor value
35
kΩ
IIAN
Analog input current
VI = VSS to VCC
0.5
5
µA
3.1.5 Timing requirements
Table 3.1.5 Timing requirements
(Vcc = 4.0V to 5.5V, Vss = AVss = 0V, Ta = –40°C to 85°C, unless otherwise noted)
Symbol
____________
tW(RESET)
Reset input “L” pulse width
Parameter
Limits
Min.
Typ.
2
Unit
Max.
µs
tC(XIN)
External clock input cycle time
100
ns
tWH(XIN)
External clock input “H” pulse width
37
ns
tWL(XIN)
External clock input “L” pulse width
37
ns
tC(CNTR)
CNTR0, CNTR1 input cycle time
(except bi-phase counter mode)
1600
ns
CNTR0, input cycle time
(bi-phase counter mode)
2000
ns
tWH(CNTR)
CNTR0, CNTR1 input “H” pulse width (except bi-phase counter mode)
800
ns
CNTR0, input “H” pulse width
(bi-phase counter mode)
1000
ns
tWL(CNTR)
CNTR0, CNTR1 input “L” pulse width (except bi-phase counter mode)
800
ns
CNTR0, input “L” pulse width
(bi-phase counter mode)
1000
ns
tL(CNTR0–TX0) Lag of CNTR0 and TX0 input edges (bi-phase counter mode)
500
ns
tC(TX0)
TX0 input cycle time
(bi-phase counter mode)
3200
ns
tWH(TX0)
TX0 input “H” pulse width
(bi-phase counter mode)
1600
ns
tWL(TX0)
TX0 input “L” pulse width
(bi-phase counter mode)
1600
ns
tWH(INT)
INT0, INT1 input “H” pulse width
460
ns
tWL(INT)
INT0, INT1 input “L” pulse width
460
ns
tC(SCLK)
Serial I/O clock input cycle time
8tc(XIN)
ns
tWH(SCLK)
Serial I/O clock input “H” pulse width
4tc(XIN)
ns
tWL(SCLK)
Serial I/O clock input “L” pulse width
4tc(XIN)
ns
tsu(SIN–SCLK)
Serial I/O clock input set up time
200
ns
tH(SCLK–SIN)
Serial I/O clock input hold time
150
ns
7630 Group User’s Manual
3-5