M32C83 Datasheet, PDF (205/527 Pages) Renesas Technology Corp – 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES

M32C/83 Group (M32C/83, M32C/83T)
16. Serial I/O (Clock Synchronous Serial I/O)
16.1 Clock Synchronous Serial I/O Mode
In clock synchronous serial I/O mode, data is transmitted and received with the transfer clock. Table 16.1
lists specifications of clock synchronous serial I/O mode. Table 16.2 lists registers to be used and settings.
Tables 16.3 to 16.5 list pin settings. When UARTi (i=0 to 4) operation mode is selected, the TxDi pin outputs
an "H" signal before transfer starts (the TxDi pin is in a high-impedance state when the N-channel open
drain output is selected). Figure 16.10 shows transmit and receive timings in clock synchronous serial I/O
mode.
Table 16.1 Clock Synchronous Serial I/O Mode Specifications
Item
Specification
Transfer Data Format
• Transfer data : 8 bits long
Transfer Clock
Transmit/Receive Control
Transmit Start Condition
• The CKDIR bit in the UiMR register (i=0 to 4) is set to "0" (internal clock selected):
fj
2(m+1) ^{fj=f1, f8, f2n(1) m :setting value of the UiBRG register 0016 to FF16.}
• The CKDIR bit is set to "1" (external clock selected) : an input from the CLKi pin
_______
_______
_______ _______
• Selected from the CTS function, RTS function or CTS/RTS function disabled
• To start transmitting, the following requirements must be met⁽²⁾:
- Set the TE bit in the UiC1 register to "1" (transmit enable)
Receive Start Condition
- Set the TI bit in the UiC1 register to "0" (data in the UiTB register)
________
_______
- Apply an "L" signal to the CTSi pin when the CTS function is selected
• To start receiving, the following requirements must be met⁽²⁾:
- Set the RE bit in the UiC1 register to "1" (receive enable)
- Set the TE bit to "1" (transmit enable)
- Set the TI bit to "0" (data in the UiTB register)
Interrupt Request Generation Timing • Transmit interrupt timing can be selected from the followings:
- The UiIRS bit in the UiC1 register is set to "0" (no data in the transmit buffer) :
when data is transferred from the UiTB register to the UARTi transmit register (transfer started)
- The UiIRS bit is set to "1" (transmission completed) :
when a data transfer from the UARTi transmit register is completed
• Receive interrupt timing
Error Detect
When data is transferred from the UARTi receive register to the UiRB register (reception completed)
• Overrun error⁽³⁾
This error occurs when the seventh bit of the next received data is read before reading
the UiRB register
Selectable Function
• CLK polarity
Transferred data is output and input on either the rising edge or falling edge of the
transfer clock
• LSB first / MSB first
Data is transmitted or received in either bit 0 or in bit 7
• Continuous receive mode
Data can be received simultaneously by reading the UiRB register
• Serial data logic inverse
This function inverses transmitted or received data logically
NOTES:
1. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15).
2. To start transmission/reception when selecting the external clock, these conditions must be met after the CKPOL
bit in the UiC0 register is set to "0" (data is transmitted on the falling edge of the transfer clock and data is received
on the rising edge) and the CLKi pin is held high ("H"), or when the CKPOL bit is set to "1" (Data is transmitted on
the rising edge of the transfer clock and data is received on the falling edge) and the CLKi pin is held low ("L").
3. If an overrun error occurs, the UiRB register is indeterminate. The IR bit in the SiRIC register does not change to "1"
(interrupt requested).
Rev. 1.31 Jan.31, 2006 ^{Page 182of} 488
REJ09B0034-0131