R01DS0012EJ0110_15 Datasheet, PDF (20/70 Pages) Renesas Technology Corp – RENESAS MCU

R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group
2. Central Processing Unit (CPU)
2. Central Processing Unit (CPU)
Figure 2.1 shows the CPU Registers. The CPU contains 13 registers. R0, R1, R2, R3, A0, A1, and FB configure a
register bank. There are two sets of register bank.
b31
R2
R3
b15
b8b7
b0
R0H (high-order of R0) R0L (low-order of R0)
R1H (high-order of R1) R1L (low-order of R1)
R2
R3
A0
A1
FB
Data registers ⁽¹⁾
Address registers ⁽¹⁾
Frame base register ⁽¹⁾
b19
b15
b0
INTBH
INTBL
The 4 high order bits of INTB are INTBH and
the 16 low order bits of INTB are INTBL.
b19
b0
PC
Interrupt table register
Program counter
b15
b0
USP
ISP
SB
b15
b0
FLG
b15
IPL
b8 b7
b0
U I OB S Z DC
Note:
1. These registers comprise a register bank. There are two register banks.
Figure 2.1 CPU Registers
User stack pointer
Interrupt stack pointer
Static base register
Flag register
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved bit
Processor interrupt priority level
Reserved bit
R01DS0012EJ0110 Rev.1.10
Jan 31, 2013
Page 20 of 67