HD49338NP_15 Datasheet, PDF (20/25 Pages) Renesas Technology Corp – CDS/PGA & 12-bit A/D Converter

HD49338NP/HNP
Electrical Characteristics (cont.)
(Unless othewide specified, Ta = 25°C, AV_DD = 3.0 V, DV_DD = 3.0 V, and R_BIAS = 33 kΩ)
• Items for CDSIN Input Mode
Item
Symbol
Min
Typ
Max
Unit Test Conditions Remarks
Consumption current (1)
IDD1
—
57
68
mA LoPwr = low
fCLK = 36 MHz
Consumption current (2)
IDD2
—
37
46
mA LoPwr = high
fCLK = 250 MHz
CCD offset tolerance range VCCD
(–100)
—
(100)
mV
Timing specifications (1)
Timing specifications (2)
tCDS1
tCDS2
—
Typ × 0.8
(1.5)
1/4fCLK
—
ns
Typ × 1.2
ns
See table 8
Timing specifications (3)
Timing specifications (4)
tCDS3
tCDS4
—
Typ × 0.8
(1.5)
1/4fCLK
—
ns
Typ × 1.2
ns
Timing specifications (5)
tCDS5
Typ × 0.85 1/2fCLK × 0.90 Typ × 1.00 ns
Timing specifications (6)
tCDS6
1
5
9
ns
Timing specifications (7)
tCDS7
11
—
—
ns
Timing specifications (8)
tCDS8
11
—
—
ns
Timing specifications (9)
tCHLD9
3
7
—
ns CL = 10 pF
Timing specifications (10)
tCOD10
—
16
24
ns
Clamp level
CLP(00)
—
(56)
—
LSB
CLP(09)
—
(128)
—
LSB
CLP(31)
—
(304)
—
LSB
PGA gain at CDS input
AGC(0)
–4.4
–2.4
–0.4
dB
AGC(256)
4.1
6.1
8.1
dB
AGC(512)
12.5
14.5
16.5
dB
AGC(768)
21.0
23.0
25.0
dB
AGC(1023)
29.4
31.4
33.4
dB
Note : Values within parentheses ( ) are for reference.
• Items for ADCIN Input Mode
Item
Symbol
Min
Typ
Consumption current (3)
IDD3
—
39
Consumption current (4)
IDD4
—
21
Timing specifications (11)
Timing specifications (12)
tADC1
tADC2
—
Typ × 0.85
(6)
1/2fADCLK
Timing specifications (13)
tADC3
Typ × 0.85
1/2fADCLK
Timing specifications (14)
tAHLD4
—
14.5
Timing specifications (15)
tAOD5
—
23.5
Input current at ADC input
IINCIN
–110
—
Clamp level at ADC input
OF2
—
(2048)
Clamp level at YIN input
OF1
—
(280)
PGA gain at ADC input
GSL(0)
0.45
0.57
GSL(256)
1.36
1.71
GSL(512)
2.27
2.86
GSL(768)
3.18
4.00
GSL(1023)
4.08
5.14
Note : Values within parentheses ( ) are for reference.
Max
49
26
—
Typ × 1.15
Typ × 1.15
—
31.5
110
—
—
0.72
2.16
3.60
5.04
6.47
Unit
mA
mA
ns
ns
ns
ns
ns
µA
LSB
LSB
Times
Times
Times
Times
Times
Test Conditions
LoPwr = low
fCLK = 36 MHz
LoPwr = high
fCLK = 20 MHz
CL = 10 pF
VIN = 1.0 V to 2.0 V
Remarks
See table 9
Rev.2.00 May 20, 2005 page 18 of 22