HD49338NP_15 Datasheet, PDF (18/25 Pages) Renesas Technology Corp – CDS/PGA & 12-bit A/D Converter

HD49338NP/HNP
Ripple (pseudo outline made by quantized error) occurres on the point which swithing the ADC output multiple bit in
parallel. When switching the several of ADC output at the same time, ripple (pseudo outline caused by miss
quantization) occurs to the image.
Differential code and gray code are recommended for this countermeasure.
Figure 10 indicates circuit block. When luminance signal changes are smoothly, the number of bit of switching digital
output bit can be reduced and easily to reduce the ripple using this function.
This function is especially effective for longer the settings of sensor more than clk = 30 kHz, and ADC output.
Figure 11 indicates the timing specifications.
10 ^{Differential SW(D5)}
ADC
2clk_DL
Standard data
control signal
(D9,D8,D7)
+
−
Carry bit
round
Standard
data
selector
Gray SW(D4)
Gray→Binary
conversion
Figure 10 Differential Code, Gray Code Circuit
10-bit
output
ADCLK
(In case of select the positive edge of ADCLK with D8)
OBP
(In case of select the positive polar)
(Beginning edge of OBP and standard edge of ADCLK should be exept ±5 ns)
Digital output
1 2 3 4 5 6 7 8 9 10 11
Differential data
Standard
data
Differential data
Figure 11 Differential Code Timing Specifications
To use differential code, complex circuit is necessary at DSP side.
From ADC
Standard data
control signal
Gray →
Binary
Carry bit
round
Standard
data
selector
2clk_DL
D9
D9
D8
D8
D7
D7
D0
D0
(1) Differential coded
(2) Gray → Binary conversion
Figure 12 Complex Circuit Example
Rev.2.00 May 20, 2005 page 16 of 22