HD49338NP_15 Datasheet, PDF (15/25 Pages) Renesas Technology Corp – CDS/PGA & 12-bit A/D Converter

HD49338NP/HNP
Serial Interface Specifications
Table 10 Serial Data Function List
Resister 0
Resister 1
DI 00 (LSB)
Low
High
Resister 2
Low
Resister 3
High
Resister 4 to 7
Test Mode (can not be used)
Low to High
DI 01
Low
Low
High
High
Low to High
DI 02
DI 03
DI 04
DI 05
Low
Low
Low
PGA gain setting (LSB) *⁵
SLP
Low: Normal operation mode
High: Sleep mode
Clamp-level [0] (LSB)
PGA gain setting *⁵
STBY
Low: Normal operation
High: Standby mode
mode
Clamp-level [1]
PGA gain setting *⁵
Output mode setting (LINV) Clamp-level [2]
Low
YC-Bias off
Gray code [0] (TEST1)
Gray code [1]
High
DI 06
PGA gain setting *⁵
Output mode setting (MINV) Clamp-level [3]
Average4, 4 lines average
DI 07
PGA gain setting *⁵
Output mode setting (TEST0) Clamp-level [4] (MSB) Gray_test [0]
DI 08
DI 09
PGA gain setting *⁵
PGA gain setting *⁵
SHA-fsel [0] (LSB)
SHA-fsel [1] (MSB)
SHAMP
frequency
HGstop-Hsel [0]
character-
istics
switching
HGstop-Hsel [1]
High-speed _{Gray_test [1]}
lead-in
cancellation
time
Gray_test [2]
DI 10
DI 11
DI 12
DI 13
PGA gain setting *⁵
SHSW-fsel [0] (LSB)
PGA gain setting *⁵
SHSW-fsel [1]
PGA gain setting (MSB) *⁵ SHSW-fsel [2]
SHSW
frequency
character-
istics
switching
HGain-Nsel [0]
HGain-Nsel [1]
High-speed _{Cannot be used. *}8
lead-in
gain
multiplication
Cannot be used. *⁸
LoPwr
Low: Normal mode
High: Low power mode
Cannot be used. *⁸
X
SHSW-fsel [3] (MSB)
SPinv,
SPSIG/SPBLK/PBLK inversion
Cannot be used. *⁸
Low
Low
High
Low
DI 14
YSEL
Low: CDSIN input mode
High: YIN input mode
DI 15 (MSB)
CSEL
Low: CDSIN input mode
High: YIN input mode
Cannot be used. *⁷
All low
OBPinv, OBP inversion Cannot be used. *⁸ Low
RESET
Low:
High:
Reset mode
Normal operation
mode
Cannot be used. *⁸
High
Cannot be used. *⁷
All low
Latches SDATA
CS
at SCK rising edge
t_INT1
f_SCK
Data is determined
at CS rising edge
t_INT2
SCK
SDATA
t_su
t_ho
DI DI DI DI DI DI DI DI DI DI DI DI DI DI DI DI
00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15
Figure 8 Serial Interface Timing Specifications
Notes: 1. 2 byte continuous communications.
2. SDATA is latched at SCK rising edge.
3. Insert 16 clocks of SCK while CS is low.
4. Data is invalid if data transmission is aborted during transmission.
5. The gain conversion table differs in the CDSIN input mode and the ADCIN input mode.
6. STBY: Reference voltage generator circuit is in the operating state.
SLP: All circuits are in the sleep state.
7. This bit is used for the IC testing, and cannot be used by the user.
Please do not set up in addition to "ALL Low".
8. This bit is used for the IC testing, and cannot be used by the user.
It is set to the state on the right of a column when RESET bit is set to low. The register
3 should transmit by setup on the right of a column.
Timing Specifications
f_SCK
t_INT1, 2
t_su
t_ho
Min

50 ns
50 ns
50 ns
Max
5 MHz



Rev.2.00 May 20, 2005 page 13 of 22