NP75P04YLG Datasheet, PDF (2/8 Pages) Renesas Technology Corp – MOS FIELD EFFECT TRANSISTOR

NP75P04YLG
Chapter Title
Electrical Characteristics (T_A = 25°C)
Item
Zero Gate Voltage Drain Current
Gate Leakage Current
Gate to Source Threshold Voltage
Forward Transfer Admittance ^∗1
Drain to Source On-state
Resistance ^∗1
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Turn-on Delay Time
Rise Time
Turn-off Delay Time
Fall Time
Total Gate Charge
Gate to Source Charge
Gate to Drain Charge
Body Diode Forward Voltage ^∗1
Reverse Recovery Time
Reverse Recovery Charge
Note: ^∗1. Pulsed
Symbol
I_DSS
I_GSS
V_GS(th)
| y_fs |
R_DS(on)1
R_DS(on)2
C_iss
C_oss
C_rss
t_d(on)
t_r
t_d(off)
t_f
Q_G
Q_GS
Q_GD
V_F(S-D)
t_rr
Q_rr
Min
−1.0
31
Typ
−1.7
63
7.7
9.3
3200
460
250
12
11
320
180
91
14
26
1.02
43
57
Max
−1
m10
−2.5
9.7
14
4800
600
450
24
27
640
440
140
1.5
Unit
μA
μA
V
S
mΩ
mΩ
pF
pF
pF
ns
ns
ns
ns
nC
nC
nC
V
ns
nC
Test Conditions
V_DS = −40 V, V_GS = 0 V
V_GS = m20 V, V_DS = 0 V
V_DS = V_GS, ID = −250 μ A
V_DS = −5 V, I_D = −37.5 A
V_GS = −10 V, I_D = −37.5 A
V_GS = −5 V, I_D = −37.5 A
V_DS = −25 V,
V_GS = 0 V,
f = 1 MHz
V_DD = −20 V, I_D = −37.5 A,
V_GS = −10 V,
R_G = 0 Ω
V_DD = −32 V,
V_GS = −10 V,
I_D = −75 A
I_F = −75 A, V_GS = 0 V
I_F = −75 A, V_GS = 0 V,
di/dt = −100 A/μ s
TEST CIRCUIT 1 AVALANCHE CAPABILITY
TEST CIRCUIT 2 SWITCHING TIME
D.U.T.
RG = 25 Ω
L
PG.
50 Ω
VDD
VGS = −20 → 0 V
IAS
ID
VDD
BVDSS
VDS
Starting Tch
TEST CIRCUIT 3 GATE CHARGE
D.U.T.
PG.
RG
VGS(−)
0
τ
τ = 1 μs
Duty Cycle ≤ 1%
RL
VDD
VGS(−)
VGS
Wave Form
10%
0
VDS(−)
90%
VDS
VDS
0
Wave Form
td(on)
VGS
90%
90%
10% 10%
tr td(off)
tf
ton
toff
D.U.T.
IG = −2 mA
RL
PG.
50 Ω
VDD
R07DS0183EJ0200 Rev.2.00
Mar 16, 2011
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