NP75P04YLG Datasheet, PDF (1/8 Pages) Renesas Technology Corp – MOS FIELD EFFECT TRANSISTOR

NP75P04YLG
MOS FIELD EFFECT TRANSISTOR
Preliminary Data Sheet
R07DS0183EJ0200
Rev.2.00
Mar 16, 2011
Description
The NP75P04YLG is P-channel MOS Field Effect Transistor designed for high current switching applications.
Features
• Low on-state resistance
⎯ R_DS(on) = 9.7 mΩ MAX. (V_GS = −10 V, I_D = −37.5 A)
⎯ R_DS(on) = 14 mΩ MAX. (V_GS = −5 V, I_D = −37.5 A)
• Logic level drive type
• Gate to Source ESD protection diode built in
• Designed for automotive application and AEC-Q101 qualified
Ordering Information
Part No.
LEAD PLATING
PACKING
NP75P04YLG -E1-AY ^∗1
Pure Sn (Tin)
Tape 2500 p/reel
NP75P04YLG -E2-AY ^∗1
Note: ^∗1. Pb-free (This product does not contain Pb in the external electrode.)
Package
8-pin HSON, Taping (E1 type)
8-pin HSON, Taping (E2 type)
<R>
<R>
Absolute Maximum Ratings (T_A = 25°C)
Item
Drain to Source Voltage (V_GS = 0 V)
Gate to Source Voltage (V_DS = 0 V)
Drain Current (DC) (T_C = 25°C)
Drain Current (pulse) ^∗1
Total Power Dissipation (T_C = 25°C)
Total Power Dissipation (T_A = 25°C) ^∗2
Channel Temperature
Storage Temperature
Single Avalanche Current ^∗3
Single Avalanche Energy ^∗3
Symbol
V_DSS
V_GSS
I_D(DC)
I_D(pulse)
P_T1
P_T2
T_ch
T_stg
I_AS
E_AS
Ratings
−40
m20
m75
m225
138
1.0
175
−55 to +175
35
123
Unit
V
V
A
A
W
W
°C
°C
A
mJ
Thermal Resistance
Channel to Case Thermal Resistance
Channel to Ambient Thermal Resistance ^∗2
R_th(ch-C)
R_th(ch-A)
1.09
150
°C/W
°C/W
Notes: ^∗1. T_C = 25°C, PW ≤ 10 μs, Duty Cycle ≤ 1%
∗_{2. Mounted on glass epoxy substrate of 40 mm x 40 mm x 0.8 mmt}
*3. Starting T_ch = 25°C, V_DD = −20 V, R_G = 25 Ω, L = 100 μH, V_GS = −20 → 0 V
The mark <R> shows major revised points.
The revised points can be easily searched by copying an "<R>" in the PDF file and specifying it in the "Find what:" field.
R07DS0183EJ0200 Rev.2.00
Mar 16, 2011
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