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M306V7MG_15 Datasheet, PDF (19/300 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER | |||
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M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
⢠Bit 5: Overflow flag (O flag)
This flag is set to â1â when an arithmetic operation resulted in overflow; otherwise, cleared to â0â.
⢠Bit 6: Interrupt enable flag (I flag)
This flag enables a maskable interrupt.
An interrupt is disabled when this flag is â0â, and is enabled when this flag is â1â. This flag is cleared to
â0â when the interrupt is acknowledged.
⢠Bit 7: Stack pointer select flag (U flag)
Interrupt stack pointer (ISP) is selected when this flag is â0â ; user stack pointer (USP) is selected
when this flag is â1â.
This flag is cleared to â0â when a hardware interrupt is acknowledged or an INT instruction of software
interrupt Nos. 0 to 31 is executed.
⢠Bits 8 to 11: Reserved area
⢠Bits 12 to 14: Processor interrupt priority level (IPL)
Processor interrupt priority level (IPL) is configured with three bits, for specification of up to eight
processor interrupt priority levels from level 0 to level 7.
If a requested interrupt has priority greater than the processor interrupt priority level (IPL), the interrupt
is enabled.
⢠Bit 15: Reserved area
The C, Z, S, and O flags are changed when instructions are executed. See the software manual for
details.
b15
IPL
b0
U I O B S Z D C Flag register (FLG)
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved area
Processor interrupt priority level
Reserved area
Figure 2.2.2 Flag register (FLG)
Rev.1.00 May 18, 2004 page 17 of 296
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